July 2024 - flashrom-gerrit - mail.coreboot.org

[S] Change in flashrom[main]: flashchips: Add Support for XMC XM25QH32C/XM25QH32D
by Anastasia Klimchuk (Code Review) 26 Jul '24

26 Jul '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83235?usp=email ) Change subject: flashchips: Add Support for XMC XM25QH32C/XM25QH32D ...................................................................... flashchips: Add Support for XMC XM25QH32C/XM25QH32D Add initial support for the SPI flash chip XM25QH32C/XM25QH32D Datasheet link: https://www.xmcwh.com/uploads/799/XM25QH32C_Ver2.1.pdf Tested with ch341a programmer: probe, read, write, erase Change-Id: Ib201ac28384b8db6539e2a82e6f90462d1393208 Signed-off-by: Kan Sun <ssunkkan(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83235 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashchips.c M include/flashchips.h 2 files changed, 39 insertions(+), 0 deletions(-) Approvals: Anastasia Klimchuk: Looks good to me, approved build bot (Jenkins): Verified diff --git a/flashchips.c b/flashchips.c index 84a3b5e..b7d378f 100644 --- a/flashchips.c +++ b/flashchips.c @@ -22126,6 +22126,44 @@ { .vendor = "XMC", + .name = "XM25QH32C/XM25QH32D", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QH32C, + .total_size = 4096, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, + .unlock = SPI_DISABLE_BLOCKPROTECT, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {2700, 3600}, + }, + + { + .vendor = "XMC", .name = "XM25QH64C", .bustype = BUS_SPI, .manufacture_id = ST_ID, diff --git a/include/flashchips.h b/include/flashchips.h index c670e3f..0f96d6a 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -850,6 +850,7 @@ #define XMC_XM25QU80B 0x5014 #define XMC_XM25QH16C 0x4015 /* Same as XM25QH16D */ #define XMC_XM25QU16C 0x5015 +#define XMC_XM25QH32C 0x4016 /* Same as XM25QH32D */ #define XMC_XM25QH128A 0x7018 #define XMC_XM25QH128C 0x4018 #define XMC_XM25QU128C 0x4118 -- To view, visit https://review.coreboot.org/c/flashrom/+/83235?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ib201ac28384b8db6539e2a82e6f90462d1393208 Gerrit-Change-Number: 83235 Gerrit-PatchSet: 2 Gerrit-Owner: Ssunk <ssunkkan(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in flashrom[main]: flashchips: Add Support for XMC XM25QH32C/XM25QH32D
by Anastasia Klimchuk (Code Review) 26 Jul '24

26 Jul '24

Attention is currently required from: Nikolai Artemiev, Ssunk, Stefan Reinauer. Anastasia Klimchuk has posted comments on this change by Ssunk. ( https://review.coreboot.org/c/flashrom/+/83235?usp=email ) Change subject: flashchips: Add Support for XMC XM25QH32C/XM25QH32D ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I will mark this unresolved, this is a comment so that no one accidentally submits before the tag. Done -- To view, visit https://review.coreboot.org/c/flashrom/+/83235?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ib201ac28384b8db6539e2a82e6f90462d1393208 Gerrit-Change-Number: 83235 Gerrit-PatchSet: 1 Gerrit-Owner: Ssunk <ssunkkan(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Ssunk <ssunkkan(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 26 Jul 2024 08:09:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Ssunk <ssunkkan(a)gmail.com>

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[S] Change in flashrom[main]: flashchips: Add Support for XMC XM25QU16C
by Anastasia Klimchuk (Code Review) 26 Jul '24

26 Jul '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83234?usp=email ) Change subject: flashchips: Add Support for XMC XM25QU16C ...................................................................... flashchips: Add Support for XMC XM25QU16C Add initial support for the SPI flash chip XM25QU16C Datasheet link: https://www.xmcwh.com/uploads/804/XM25QU16C_%20Ver1.8.pdf Tested with ch341a programmer: probe, read, write, erase Change-Id: I0989b5dd239dd32f93e1a338a70e5d7279127d8d Signed-off-by: Kan Sun <ssunkkan(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83234 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashchips.c M include/flashchips.h 2 files changed, 39 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index 0ae5f46..84a3b5e 100644 --- a/flashchips.c +++ b/flashchips.c @@ -22088,6 +22088,44 @@ { .vendor = "XMC", + .name = "XM25QU16C", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QU16C, + .total_size = 2048, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, + .unlock = SPI_DISABLE_BLOCKPROTECT, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {1650, 1950}, + }, + + { + .vendor = "XMC", .name = "XM25QH64C", .bustype = BUS_SPI, .manufacture_id = ST_ID, diff --git a/include/flashchips.h b/include/flashchips.h index 8961754..c670e3f 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -849,6 +849,7 @@ #define XMC_XM25QU64C 0x4117 #define XMC_XM25QU80B 0x5014 #define XMC_XM25QH16C 0x4015 /* Same as XM25QH16D */ +#define XMC_XM25QU16C 0x5015 #define XMC_XM25QH128A 0x7018 #define XMC_XM25QH128C 0x4018 #define XMC_XM25QU128C 0x4118 -- To view, visit https://review.coreboot.org/c/flashrom/+/83234?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0989b5dd239dd32f93e1a338a70e5d7279127d8d Gerrit-Change-Number: 83234 Gerrit-PatchSet: 2 Gerrit-Owner: Ssunk <ssunkkan(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in flashrom[main]: flashchips: Add Support for XMC XM25QU16C
by Anastasia Klimchuk (Code Review) 26 Jul '24

26 Jul '24

Attention is currently required from: Nikolai Artemiev, Ssunk, Stefan Reinauer. Anastasia Klimchuk has posted comments on this change by Ssunk. ( https://review.coreboot.org/c/flashrom/+/83234?usp=email ) Change subject: flashchips: Add Support for XMC XM25QU16C ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Ok, I know,thanks Done -- To view, visit https://review.coreboot.org/c/flashrom/+/83234?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0989b5dd239dd32f93e1a338a70e5d7279127d8d Gerrit-Change-Number: 83234 Gerrit-PatchSet: 1 Gerrit-Owner: Ssunk <ssunkkan(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Ssunk <ssunkkan(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 26 Jul 2024 08:06:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ssunk <ssunkkan(a)gmail.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[M] Change in flashrom[main]: flashchips: Add support for MXIC MX25U25645G
by Anastasia Klimchuk (Code Review) 26 Jul '24

26 Jul '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/82777?usp=email ) Change subject: flashchips: Add support for MXIC MX25U25645G ...................................................................... flashchips: Add support for MXIC MX25U25645G The MX25U25645G has been tested by ch341a programmer : read, write, erase and wp. We have tested --wp-enable, --wp-disable, --wp-list and --wp-range commands for write-protect feature. MX25U25645G datasheet is available at the following URL: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8738/MX25U25645G,%201.8… Change-Id: I8641f36e1909274629690fc243be46281a21360d Signed-off-by: DanielZhang <danielzhang(a)mxic.com.cn> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82777 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashchips.c M include/flashchips.h 2 files changed, 57 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index c34bafb..0ae5f46 100644 --- a/flashchips.c +++ b/flashchips.c @@ -11152,6 +11152,62 @@ { .vendor = "Macronix", + .name = "MX25U25645G", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25U25635F, + .total_size = 32768, + .page_size = 256, + /* OTP: 1024B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_4BA | FEATURE_CFGR | FEATURE_SCUR, + .tested = TEST_OK_PREWB, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = SPI_BLOCK_ERASE_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_5C, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_DC, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6 is quad enable */ + .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD, + .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ + .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {CONFIG, 3, OTP}, + .wps = {SECURITY, 7, OTP}, /* This bit is set by WPSEL command */ + }, + .decode_range = DECODE_RANGE_SPI25, + }, + + { + .vendor = "Macronix", .name = "MX25U3235E/F", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, diff --git a/include/flashchips.h b/include/flashchips.h index a43a0f9..8961754 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -534,7 +534,7 @@ #define MACRONIX_MX25U3235E 0x2536 /* Same as MX25U6435F */ #define MACRONIX_MX25U6435E 0x2537 /* Same as MX25U6435F */ #define MACRONIX_MX25U12835E 0x2538 /* Same as MX25U12835F */ -#define MACRONIX_MX25U25635F 0x2539 /* Same as MX25U25643G */ +#define MACRONIX_MX25U25635F 0x2539 /* Same as MX25U25643G, MX25U25645G */ #define MACRONIX_MX25U51245G 0x253a #define MACRONIX_MX25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */ #define MACRONIX_MX25L6495F 0x9517 -- To view, visit https://review.coreboot.org/c/flashrom/+/82777?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I8641f36e1909274629690fc243be46281a21360d Gerrit-Change-Number: 82777 Gerrit-PatchSet: 4 Gerrit-Owner: DZ <danielzhang(a)mxic.com.cn> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in flashrom[main]: flashchips: Add support for MXIC MX25U25645G
by Anastasia Klimchuk (Code Review) 26 Jul '24

26 Jul '24

Attention is currently required from: DZ, Nikolai Artemiev, Stefan Reinauer. Anastasia Klimchuk has posted comments on this change by DZ. ( https://review.coreboot.org/c/flashrom/+/82777?usp=email ) Change subject: flashchips: Add support for MXIC MX25U25645G ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > Wait until the tag v1.4.0 done and after that the patch can be submitted. ETA 26 July. […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/82777?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I8641f36e1909274629690fc243be46281a21360d Gerrit-Change-Number: 82777 Gerrit-PatchSet: 3 Gerrit-Owner: DZ <danielzhang(a)mxic.com.cn> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: DZ <danielzhang(a)mxic.com.cn> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 26 Jul 2024 08:02:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[S] Change in flashrom[main]: how_to_add_new_chip: Add a section for feature bits and WRSR handling
by Anastasia Klimchuk (Code Review) 26 Jul '24

26 Jul '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/82908?usp=email ) Change subject: how_to_add_new_chip: Add a section for feature bits and WRSR handling ...................................................................... how_to_add_new_chip: Add a section for feature bits and WRSR handling Feature bits are too complicated to understand if we only read the codes/datasheets. Add a new section in how_to_add_new_chip to add more details about each feature bits. Add the detailed explanation for WRSR handling first. If this new section looks good, I'll try to add some more sections in further commits. BUG=b:345154585 TEST=meson compile -C builddir and view the doc. Change-Id: I34c20933a375380c8702f79ac637595cd3466000 Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82908 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M doc/contrib_howtos/how_to_add_new_chip.rst 1 file changed, 26 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/doc/contrib_howtos/how_to_add_new_chip.rst b/doc/contrib_howtos/how_to_add_new_chip.rst index b046ac3..8aad324 100644 --- a/doc/contrib_howtos/how_to_add_new_chip.rst +++ b/doc/contrib_howtos/how_to_add_new_chip.rst @@ -96,12 +96,36 @@ * ``.page_size`` is really hard. Please read this `long explanation <https://mail.coreboot.org/pipermail/flashrom/2013-April/010817.html>`_, or ignore it for now and set it to 256. -* We encode various features of flash chips in a bitmask named ``.feature_bits``. - Available options can be found in ``include/flash.h``, look for macros defined by the pattern ``#define FEATURE_XXX``. * ``.tested`` is used to indicate if the code was tested to work with real hardware, its possible values are defined in ``include/flash.h``. Without any tests it should be set to ``TEST_UNTESTED``. See also another doc :doc:`how_to_mark_chip_tested`. +Feature Bits +============ + +We encode various features of flash chips in a bitmask named ``.feature_bits``. +Available options can be found in ``include/flash.h``, look for macros defined by the pattern ``#define FEATURE_XXX``. + +Some of the feature bits have more detailed docs, see below. + +Write-Status-Register (WRSR) Handling +------------------------------------- + +The Write Status Register (WRSR) is used exclusively in SPI flash chips to configure various settings within the flash chip, +including write protection and other features. +The way WRSR is accessed varies between SPI flash chips, leading to the need for these feature bits. + +* ``FEATURE_WRSR_EWSR`` + indicates that we need an **Enable-Write-Status-Register** (EWSR) instruction which opens the status register for the + immediately-followed next WRSR instruction. Usually, the opcode is **0x50**. + +* ``FEATURE_WRSR_WREN`` + indicates that we need an **Write-Enable** (WREN) instruction to set the Write Enable Latch (WEL) bit. The WEL bit + must be set prior to every WRSR command. Usually, the opcode is **0x06**. + +* ``FEATURE_WRSR_EITHER`` + indicates that either EWSR or WREN is supported in this chip. + Operations ========== -- To view, visit https://review.coreboot.org/c/flashrom/+/82908?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I34c20933a375380c8702f79ac637595cd3466000 Gerrit-Change-Number: 82908 Gerrit-PatchSet: 4 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in flashrom[main]: how_to_add_new_chip: Add a section for feature bits and WRSR handling
by Anastasia Klimchuk (Code Review) 26 Jul '24

26 Jul '24

Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen, Thomas Heijligen. Anastasia Klimchuk has posted comments on this change by Hsuan-ting Chen. ( https://review.coreboot.org/c/flashrom/+/82908?usp=email ) Change subject: how_to_add_new_chip: Add a section for feature bits and WRSR handling ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > Wait until the tag v1.4.0 done and after that the patch can be submitted. ETA 26 July. […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/82908?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I34c20933a375380c8702f79ac637595cd3466000 Gerrit-Change-Number: 82908 Gerrit-PatchSet: 3 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Fri, 26 Jul 2024 08:01:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[M] Change in flashrom[main]: flashchips: Add chip models GD25LB256F/GD25LR256F
by Anastasia Klimchuk (Code Review) 26 Jul '24

26 Jul '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83254?usp=email ) Change subject: flashchips: Add chip models GD25LB256F/GD25LR256F ...................................................................... flashchips: Add chip models GD25LB256F/GD25LR256F GD25LB256F: 1.8V 256Mbit https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230926/DS-0… GD25LR256F: 1.8V 256Mbit with RPMC. https://www.gigadevice.com/message-board?cid=39&id=3171&file_type=Datasheet… Tested Erase, write, read, and protection. Change-Id: I0fbd270a57999d4131816c48470588bb7ec22d37 Signed-off-by: Victor <vlim(a)gigadevice.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83254 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashchips.c 1 file changed, 57 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved Nikolai Artemiev: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index 1a7954c..c34bafb 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6953,6 +6953,63 @@ }, { + .vendor = "GigaDevice", + .name = "GD25LB256F/GD25LR256F", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25LQ255E, + .total_size = 32768, + .page_size = 256, + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT2 | FEATURE_4BA, + .tested = TEST_OK_PREWB, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = SPI_BLOCK_ERASE_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_5C, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_DC, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, + .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, /* TODO: 2nd status reg (read with 0x35) */ + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1650, 2000}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like TB */ + .cmp = {STATUS2, 6, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, + }, + + { .vendor = "GigaDevice", .name = "GD25LR512ME", .bustype = BUS_SPI, -- To view, visit https://review.coreboot.org/c/flashrom/+/83254?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0fbd270a57999d4131816c48470588bb7ec22d37 Gerrit-Change-Number: 83254 Gerrit-PatchSet: 4 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in flashrom[main]: flashchips: Add chip models GD25LB256F/GD25LR256F
by Anastasia Klimchuk (Code Review) 26 Jul '24

26 Jul '24

Attention is currently required from: Stefan Reinauer, Victor Lim. Anastasia Klimchuk has posted comments on this change by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/83254?usp=email ) Change subject: flashchips: Add chip models GD25LB256F/GD25LR256F ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > I am leaving this comment unresolved, so that the patch won't be accidentally submitted before the t […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/83254?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0fbd270a57999d4131816c48470588bb7ec22d37 Gerrit-Change-Number: 83254 Gerrit-PatchSet: 3 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Fri, 26 Jul 2024 07:59:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Victor Lim <vlim(a)gigadevice.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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