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Change subject: ch347_spi: Add spi clock frequency selection
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10:
I have a question, which is not for this patch, but more for the future.
Would any of you be interested to write a unit test for this programmer? The sibling ch341a_spi already has a unit test which covers init-probe-shutdown.
Unit test is not interacting with any hardware, test is running flashrom code. It reduces the risk of breakages, and unit tests run on CI (Jenkins). When a patch gets Verified+1 it means all unit tests pass.
I think the existing test for ch341a_spi will have a lot in common with the ch347_spi test.
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Change subject: doc: Release notes for version 1.4.0
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Submit after tag v1.4.0 done
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Change subject: doc: Release notes for version 1.4.0
......................................................................
doc: Release notes for version 1.4.0
Change-Id: Ie5597f1c3ae9289e424f54c2d313fef8efbdf1a0
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
M doc/release_notes/index.rst
A doc/release_notes/v_1_4.rst
2 files changed, 303 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/59/83359/1
diff --git a/doc/release_notes/index.rst b/doc/release_notes/index.rst
index a8ef58f..1d2e0d9 100644
--- a/doc/release_notes/index.rst
+++ b/doc/release_notes/index.rst
@@ -4,4 +4,5 @@
.. toctree::
:maxdepth: 1
+ v_1_4
v_1_3
diff --git a/doc/release_notes/v_1_4.rst b/doc/release_notes/v_1_4.rst
new file mode 100644
index 0000000..1cc34b5
--- /dev/null
+++ b/doc/release_notes/v_1_4.rst
@@ -0,0 +1,302 @@
+================
+v1.4 (July 2024)
+================
+
+Release notes for flashrom version 1.4.0.
+
+Known issue
+===========
+
+Fix AMD programmer (sb600spi.c) for Promontory and chips >16MB size
+
+https://ticket.coreboot.org/issues/370
+
+Major updates
+=============
+
+Optimised erase and write logic
+-------------------------------
+
+Significant performance improvements with new logic which is based on: the optimal selection of erase blocks for the given logical layout,
+available erase functions, and size of memory area to erase/write.
+
+**Legacy code path still exists in the source tree, but it will be deleted by the next release.**
+
+Optimised delays logic
+----------------------
+
+Optimised logic and refactorings of delays functionality, in particular for SPI chips.
+
+* Calibration loop is not used anymore, except for DOS
+* Removed unconditional 1 second delay for SPI chips
+* Lower the sleep vs delay threshold to 0.1 seconds
+* Tree-wide refactorings around programmer_delay and internal_delay
+
+Documentation is in the git tree
+--------------------------------
+
+Note: the migration process is half way.
+
+Docs are available in the same repository as the code, in ``doc/`` directory.
+
+Website content is automatically generated from docs in the git tree.
+
+**Patches with code changes and new features can (and should) update documentation in the same patch, which makes it a lot easier to maintain up-to-date docs.**
+
+Our current two build systems, meson and make, are on par
+---------------------------------------------------------
+
+Both build systems support the same platforms and both are documented (however, unit tests only supported with meson).
+
+**This is the last release with two build systems. With the next release, make and Makefile will no longer be supported, and we will have one build system: meson.**
+
+Write-protect updates
+---------------------
+
+* Support reading security register
+* Support reading/writing configuration register
+* More range functions (with different block sizes and handling of CMP bit)
+
+Protected regions support
+-------------------------
+
+* Support to allow programmers to handle protected regions on the flash.
+* get_region() function is added so that programmers can expose access permissions for multiple regions within the flash.
+* A get_region() implementation is added for the ichspi driver
+
+Chipset support added
+=====================
+
+* Tiger Lake
+* Emmitsburg Chipset SKU
+* Meteor Lake-P/M
+* Panther Lake-U/H 12Xe
+* Panther Lake-H 4Xe
+
+Chip models support added or updated
+====================================
+
+New models support
+------------------
+
+* AT25DF011
+
+* B.25D80A
+* B25Q64AS
+
+* GD25LB128E/GD25LR128E
+* GD25LB256E
+* GD25LF128E
+* GD25Q127C/GD25Q128E
+* GD25LQ255E
+* GD25LR256E
+* GD251R512ME
+
+* IS25LP016
+* IS25LQ016
+* IS25WP016
+* IS25WP020
+* IS25WP040
+* IS25WP080
+* IS25WQ040
+
+* MX25L1633E
+* MX25L1636E
+* MX25L3239E
+* MX25L3255E
+* MX25L3273F
+* MX25L6473F
+* MX25L6436E/MX25L6445E/MX25L6465E
+* MX25L6473E
+* MX25L12850F
+* MX77L25650F
+* MX25R2035F
+* MX25R4035F
+* MX25R8035F
+* MX25U25643G
+* MX25V16066
+
+* P25Q06H
+* P25Q11H
+* P25Q21H
+
+* W25Q16JV_M
+
+* XM25QH128A
+* XM25QH80B
+* XM25QH16C/XM25QH16D
+* XM25QU80B
+* XM25RU256C
+
+* XT25F02E
+* XT25F64B
+* XT25F128B
+
+* ZD25D20
+
+Added write-protect support
+---------------------------
+
+* EN25QH32
+* EN25QH64
+
+* MX25L3206E/MX25L3208E
+* MX25L6405
+* MX25L6405D
+* MX25L6406E/MX25L6408E
+* MX25L12833F
+* MT25QL512
+* MX25R1635F
+* MX25R1635F
+* MX25U25643G
+* MX25V1635F
+* MX25V4035F
+* MX25V8035F
+
+* N25Q032..1E
+* N25Q032..3E
+* N25Q064..1E
+* N25Q064..3E
+
+* W25Q16.V
+* W25Q32BV/W25Q32CV/W25Q32DV
+* W25Q32FV
+* W25Q32JV
+* W25Q32BW/W25Q32CW/W25Q32DW
+* W25Q32FW
+* W25Q32JW...Q
+* W25Q32JW...M
+* W25Q64JW...M
+* W25Q256JW_DTR
+* W25Q512NW-IM
+* W25X05
+* W25X10
+* W25X16
+* W25X20
+* W25X32
+* W25X40
+* W25X64
+* W25X80
+
+Marked as tested
+----------------
+
+* AM29LV040B
+
+* AT29C010A
+
+* FM25F01
+* FM25Q16
+
+* MT25QL128
+
+* S25FL128L
+
+* W25Q128.V
+
+* XM25QH64C
+* XM25QH256C
+* XM25QU256C
+
+Programmers support added or updated
+====================================
+
+* New programmer for ASM106x SATA controllers
+* New programmer for WCH CH347, supports CH347T and CH347F packaging.
+
+* buspirate: Add option for setting the aux pin
+* jlink_spi: add cs=tms option to jlink_spi programmer
+* raiden: Support target index with generic REQ_ENABLE
+* buspirate_spi: add support for hiz output with pullups=off
+* serprog: Add support for multiple SPI chip selects
+
+Utilities
+=========
+
+* Bash completion (enabled by default with command line interface)
+
+* CI checks for Signed-off-by line in commit message
+
+* CI builds documentation
+
+Unit tests
+==========
+
+Added coverage for erase and write logic
+----------------------------------------
+
+20 test cases for each operation, with various logical layouts and chip memory states, and additional 6 for each, with protected regions configured.
+The test for erase and write is set up so that new test cases can be added whenever needed.
+
+selfcheck
+---------
+
+selfcheck is now also implemented as a unit test.
+
+selfcheck provides critical sanity checks for the programmer table, board matches table, and array of flashchip definitions.
+
+Note that selfcheck currently, by default, still runs on flashrom init, because at the moment we can't run unit tests on all supported platforms,
+and we don't have continuous integration for all platforms.
+
+This gives an opportunity for performance improvement for developers or companies who build their own flashrom binary and, importantly,
+can run unit tests with the build (Linux, BSD). For their own binary, it is possible to disable selfcheck on init and save some time
+(**under their own responsibility to run unit tests**).
+
+Coverage report
+---------------
+
+Unit tests coverage report can be generated with gcov or lcov / llvm.
+
+ch341a_spi test
+---------------
+
+Unit test which covers initialization-probing-shutdown of ch341a_spi.
+
+Reduces the risk of breakage for the very popular programmer.
+
+Write-protect
+-------------
+
+Added coverage for write-protect operation
+
+Some of the other misc fixes and improvements
+=============================================
+
+* bitbang_spi.c: Fix unchecked heap allocation
+* writeprotect.c: skip unnecessary writes
+* writeprotect.c: refuse to work with chip if OTP WPS == 1
+* flashrom.c: Drop redundant chip read validation in verify_range()
+* ichspi: Clear Fast SPI HSFC register before HW seq operation
+* ichspi: Fix number of bytes for HW seq operations
+* writeprotect,ichspi,spi25: handle register access constraints
+* tree/: Make heap alloc checks err msg consistent
+* flashrom.c: Replace 'exit(1)' leaks with return codes on err paths
+* flashrom: Check for flash access restricitons in read_flash()
+* flashrom: Check for flash access restricitons in verify_range()
+* flashrom: Check for flash access restricitons in write_flash()
+* flashrom: Check for flash access restrictions in erase path
+* flashrom: Use WP-based unlocking on opaque masters
+* ni845x_spi: Fix signed - unsigned comparisons
+* flashrom: only perform WP unlock for write/erase operations
+* serial: Fix sp_flush_incoming for serprog TCP connections
+* Makefile,meson.build: Add support for Sphinx versions prior to 4.x
+* Makefile: Fix cleanup for Sphinx versions prior to 4.x
+* Makefile: Fix version string for non-Git builds
+* serprog protocol: Add SPI Mode and CS Mode commands
+* util/list_yet_unsupported_chips.h: Fix path
+* flashrom_udev.rules: Add rule for CH347
+* Add documentation for pico-serprog
+* cli_classic: Defer flashrom_init calibration until after options parsing
+* hwaccess_x86_io: Fix Android compilation with bionic libc
+
+Download
+========
+
+flashrom 1.4 can be downloaded in various ways:
+
+Anonymous checkout from the git repository at https://review.coreboot.org/flashrom.git (tag v1.4.0)
+
+A tarball is available for download at
+<TODO add link>,
+
+fingerprint: <TODO add>
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Change subject: flashchips: Add chip models GD25LB256F/GD25LR256F
......................................................................
Patch Set 3: Code-Review+2
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Change subject: ch347_spi: Add spi clock frequency selection
......................................................................
Patch Set 10:
(2 comments)
File doc/classic_cli_manpage.rst:
https://review.coreboot.org/c/flashrom/+/82776/comment/6f75932c_880155bd?us… :
PS9, Line 1025:
> remove trailing space
Done
https://review.coreboot.org/c/flashrom/+/82776/comment/b8cbb8e3_bbf580dc?us… :
PS9, Line 1028: -p
> Remove one `-p`, you have double of them
Done
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Change subject: ch347_spi: Add spi clock frequency selection
......................................................................
Patch Set 9:
(2 comments)
File doc/classic_cli_manpage.rst:
https://review.coreboot.org/c/flashrom/+/82776/comment/b08d8801_d6d8c391?us… :
PS9, Line 1025:
remove trailing space
https://review.coreboot.org/c/flashrom/+/82776/comment/6e6e48fd_d72609ea?us… :
PS9, Line 1028: -p
Remove one `-p`, you have double of them
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Change subject: flashchips: Add chip models GD25LB256F/GD25LR256F
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Victor, as I said in the other comment, this patch is ready but it needs to wait until the tag v1.4.0.
You can prepare more patches if you want, and they can be reviewed. Everything that is ready will be submitted after the tag v1.4.0
If you decide to send more patches, you can create more git branches in your local repository, and prepare new commits each in its own branch.
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Change subject: flashchips: Add chip models GD25LB256F/GD25LR256F
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Patchset:
PS3:
Wait until the tag v1.4.0 done and after that the patch can be submitted. ETA 26 July.
https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/UUDQ…
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