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Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/flashrom/+/83144?usp=email )
Change subject: ichspi: Add support for Panther Lake
......................................................................
Patch Set 2:
(1 comment)
File include/programmer.h:
https://review.coreboot.org/c/flashrom/+/83144/comment/2a424fe4_06be122a?us… :
PS1, Line 364: /* All chipsets after METEOR_LAKE should support checking BIOS_BM to get read/write access to of FREG0~15 */
> > We attempted to move METEOR_LAKE to the bottom of the ich_chipset enum, but this patch reveals that many usages still rely on the existing order:
> > ```
> > case CHIPSET_METEOR_LAKE:
> > case CHIPSET_PANTHER_LAKE:
> > case CHIPSET_APOLLO_LAKE:
> > case CHIPSET_GEMINI_LAKE:
> > case CHIPSET_JASPER_LAKE:
> > case CHIPSET_ELKHART_LAKE:
> > ```
> >
> > Based on your expertise, which order would be more logical and maintainable? Could you provide insights on the factors that should be considered when determining the ideal order?
>
> this is fine, PTL is post MTL hence, the Flash range between 0-15 actually applies for PTL as well. The only problem that was existed, now fixed with CB:83143.
```
static unsigned int ich_get_defined_region_count(void) {
return (ich_generation >= CHIPSET_METEOR_LAKE) ? 16 : 8;
}
```
this is what i meant should be enough to cover PTL as well (post MTL)
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Attention is currently required from: Anastasia Klimchuk, Hsuan Ting Chen, Hsuan-ting Chen, Sam McNally.
Hello Anastasia Klimchuk, Hsuan Ting Chen, Hsuan-ting Chen, Sam McNally, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/83144?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Code-Review+1 by Sam McNally, Verified+1 by build bot (Jenkins)
Change subject: ichspi: Add support for Panther Lake
......................................................................
ichspi: Add support for Panther Lake
This patch adds Panther Lake support into flashrom.
BUG=b:347669091
TEST=Flashrom is able to detect PTL SPI DID and show chipset name as
below:
> flashrom --flash-name
....
Found chipset "Intel Panther Lake-U/H 12Xe".
....
> flashrom -p internal --ifd -i fd -i bios -r /tmp/bios.rom
....
Reading ich_descriptor... done.
Assuming chipset 'Panther Lake'.
Using regions: "bios", "fd".
Reading flash... done.
SUCCESS
Change-Id: I99cd8eb7cbb11381f8e8455b06cf90b9db77d8f0
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M chipset_enable.c
M ich_descriptors.c
M ichspi.c
M include/programmer.h
M util/ich_descriptors_tool/ich_descriptors_tool.c
5 files changed, 35 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/44/83144/2
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Change subject: flashchips: add support for MX77U51250F chip
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Daniel, is it possible to get the datasheet for MX77U51250F ? I would check the values in this patch […]
Hi, our Macronix product manager will discuss this issue recently.
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Change subject: ichspi: Add support for Panther Lake
......................................................................
Patch Set 1:
(1 comment)
File include/programmer.h:
https://review.coreboot.org/c/flashrom/+/83144/comment/87f97787_2921acf2?us… :
PS1, Line 364: /* All chipsets after METEOR_LAKE should support checking BIOS_BM to get read/write access to of FREG0~15 */
> We attempted to move METEOR_LAKE to the bottom of the ich_chipset enum, but this patch reveals that many usages still rely on the existing order:
> ```
> case CHIPSET_METEOR_LAKE:
> case CHIPSET_PANTHER_LAKE:
> case CHIPSET_APOLLO_LAKE:
> case CHIPSET_GEMINI_LAKE:
> case CHIPSET_JASPER_LAKE:
> case CHIPSET_ELKHART_LAKE:
> ```
>
> Based on your expertise, which order would be more logical and maintainable? Could you provide insights on the factors that should be considered when determining the ideal order?
this is fine, PTL is post MTL hence, the Flash range between 0-15 actually applies for PTL as well. The only problem that was existed, now fixed with CB:83143.
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Change subject: flashchips: Set default wp test status for chips with custom config
......................................................................
Patch Set 2:
(2 comments)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/83132/comment/7b1368f8_049b1985?us… :
PS1, Line 2651: .tested = {.probe = NT, .read = NT, .erase = NT, .write = BAD, .wp = NT},
> The chip seems to have only sector-based write protection and no block protection. […]
Thank you so much for catching! I put NA here (and also in the other chip).
https://review.coreboot.org/c/flashrom/+/83132/comment/0f952d8b_947270fb?us… :
PS1, Line 3720: .tested = {.probe = OK, .read = OK, .erase = BAD, .write = BAD, .wp = NT},
> It's [this chip](https://pdf1.alldatasheet.com/datasheet-pdf/view/57384/CATALYST/CAT28…. […]
Done
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to look at the new patch set (#2).
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Verified+1 by build bot (Jenkins)
Change subject: flashchips: Set default wp test status for chips with custom config
......................................................................
flashchips: Set default wp test status for chips with custom config
Without this, default value is the first in enum, which is OK. While
in reality, for the chips in the patch block-protection is not
available, so should be NA.
wp test status support was introduced later than the others, so old
chips don't have this field initialised.
Change-Id: I6ed8e04cd215865dc6a7d9415634dedbe3014ab5
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
M flashchips.c
1 file changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/32/83132/2
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Change subject: ichspi: Add support for Panther Lake
......................................................................
Patch Set 1:
(1 comment)
File include/programmer.h:
https://review.coreboot.org/c/flashrom/+/83144/comment/fb6f2dc4_00f9227a?us… :
PS1, Line 364: /* All chipsets after METEOR_LAKE should support checking BIOS_BM to get read/write access to of FREG0~15 */
We attempted to move METEOR_LAKE to the bottom of the ich_chipset enum, but this patch reveals that many usages still rely on the existing order:
```
case CHIPSET_METEOR_LAKE:
case CHIPSET_PANTHER_LAKE:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_JASPER_LAKE:
case CHIPSET_ELKHART_LAKE:
```
Based on your expertise, which order would be more logical and maintainable? Could you provide insights on the factors that should be considered when determining the ideal order?
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