June 2024 - flashrom-gerrit - mail.coreboot.org

[S] Change in flashrom[main]: flashchips: add support for MX77U51250F chip
by Bora Guvendik (Code Review) 18 Jun '24

18 Jun '24

Attention is currently required from: Anastasia Klimchuk, DZ, Nikolai Artemiev, Stefan Reinauer. Bora Guvendik has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/flashrom/+/82626?usp=email ) Change subject: flashchips: add support for MX77U51250F chip ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > I see. I will try! […] Yes, I have the datasheet and chip. We were able to flash with this patch. -- To view, visit https://review.coreboot.org/c/flashrom/+/82626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I2c2e94f01dc63f60cf636bc6afe1f033e2a6f83c Gerrit-Change-Number: 82626 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: DZ <danielzhang(a)mxic.com.cn> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: DZ <danielzhang(a)mxic.com.cn> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Tue, 18 Jun 2024 17:58:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[L] Change in flashrom[main]: Add support for more XMC series
by Anastasia Klimchuk (Code Review) 16 Jun '24

16 Jun '24

Attention is currently required from: Nikolai Artemiev, Ssunk, Stefan Reinauer. Anastasia Klimchuk has posted comments on this change by Ssunk. ( https://review.coreboot.org/c/flashrom/+/83089?usp=email ) Change subject: Add support for more XMC series ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Kankan, thank you for your patch, appreciate adding support for so many chip models! I have few questions: 1) Could you please split your commit into smaller ones? It can be one model per commit, also can be a group of models if they are related. And then smaller commits can be reviewed and finished one by one. 2) Do you have links to datasheets? 3) I noticed that test status for the models in this patch is different, some of them are tested, some are not. Does the status corresponds to what you were testing? Thanks! -- To view, visit https://review.coreboot.org/c/flashrom/+/83089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I4e4eec6553407466b4b84969a806f046f6bddcbf Gerrit-Change-Number: 83089 Gerrit-PatchSet: 1 Gerrit-Owner: Ssunk <ssunkkan(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Ssunk <ssunkkan(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Sun, 16 Jun 2024 08:41:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in flashrom[main]: MAINTAINERS: Add Anastasia Klimchuk for CI script
by Anastasia Klimchuk (Code Review) 16 Jun '24

16 Jun '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83063?usp=email ) Change subject: MAINTAINERS: Add Anastasia Klimchuk for CI script ...................................................................... MAINTAINERS: Add Anastasia Klimchuk for CI script Change-Id: I0aa30ffc69117e933e1bfbb07a456b1709693c59 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83063 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Peter Marheine <pmarheine(a)chromium.org> --- M MAINTAINERS 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: Peter Marheine: Looks good to me, approved build bot (Jenkins): Verified diff --git a/MAINTAINERS b/MAINTAINERS index f4e0c9a..a897a12 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -195,6 +195,11 @@ S: Maintained F: util/flashrom.bash-completion.tmpl +CONTINUOUS INTEGRATION SCRIPT +M: Anastasia Klimchuk <aklm(a)chromium.org> +S: Maintained +F: test_build.sh + FLASHROM TESTER M: Hsuan Ting Chen <roccochen(a)google.com> R: Evan Benn <evanbenn(a)gmail.com> -- To view, visit https://review.coreboot.org/c/flashrom/+/83063?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0aa30ffc69117e933e1bfbb07a456b1709693c59 Gerrit-Change-Number: 83063 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in flashrom[main]: flashchips: Add support for chip model GD25LB128E/GD25LR128E
by Anastasia Klimchuk (Code Review) 16 Jun '24

16 Jun '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83012?usp=email ) Change subject: flashchips: Add support for chip model GD25LB128E/GD25LR128E ...................................................................... flashchips: Add support for chip model GD25LB128E/GD25LR128E Adding GD25LB128E/GD25LR128E to flashchip.c These part # sharing the same ID, form, fit, function, produced with different process node: 1.8V 128Mbit Datasheet Link: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230926/DS-0… https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-0… https://www.gigadevice.com/message-board?cid=39&id=3004&file_type=Datasheet… Change-Id: I8e8ad6bd69e2159b7cc2b64a7a8c7fcb1399294d Signed-off-by: Victor Lim <vlim(a)gigadevice.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83012 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashchips.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index 86ebce3..10071fd 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6587,7 +6587,7 @@ { .vendor = "GigaDevice", - .name = "GD25LQ128C/GD25LQ128D/GD25LQ128E", + .name = "GD25LQ128E/GD25LB128E/GD25LR128E/GD25LQ128D/GD25LQ128C", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25LQ128CD, -- To view, visit https://review.coreboot.org/c/flashrom/+/83012?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I8e8ad6bd69e2159b7cc2b64a7a8c7fcb1399294d Gerrit-Change-Number: 83012 Gerrit-PatchSet: 3 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in flashrom[main]: how_to_add_new_chip: Add a section for feature bits and WRSR handling
by Anastasia Klimchuk (Code Review) 15 Jun '24

15 Jun '24

Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen, Thomas Heijligen. Anastasia Klimchuk has posted comments on this change by Hsuan-ting Chen. ( https://review.coreboot.org/c/flashrom/+/82908?usp=email ) Change subject: how_to_add_new_chip: Add a section for feature bits and WRSR handling ...................................................................... Patch Set 1: (5 comments) File doc/contrib_howtos/how_to_add_new_chip.rst: https://review.coreboot.org/c/flashrom/+/82908/comment/bfe99749_cb6f2201?us… : PS1, Line 105: Feature Bits : ------------- This can be on the same level as "Properties", especially because you have future plans to gradually upgrade it. Which means, change the level of the heading, use `=` instead of `-`, and when you generate the doc check that Feature Bits heading on the same level as Properties as Operations. https://review.coreboot.org/c/flashrom/+/82908/comment/37d107af_3b345cad?us… : PS1, Line 108: The ``.feature_bits`` field in a chip definition encodes various features using a bitmask. : Here are some of the selected feature bits that need to be highlighted: With this, we don't need an item in a list inside Properties. Remove the item from Properties list, and merge the description from there and here, for example like this: > We encode various features of flash chips in a bitmask named ``.feature_bits``. Available options can be found in ``include/flash.h``, look for macros defined by the pattern ``#define FEATURE_XXX``. Some of the feature bits have more detailed docs, see below. https://review.coreboot.org/c/flashrom/+/82908/comment/d65ef3de_86ef620f?us… : PS1, Line 111: Write-Status-Register (WRSR) Handling : ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This header also goes on level up, use `-` https://review.coreboot.org/c/flashrom/+/82908/comment/46a3e8b5_fb4220c5?us… : PS1, Line 113: : ``FEATURE_WRSR_EWSR``, ``FEATURE_WRSR_WREN``, and ``FEATURE_WRSR_EITHER``. These bits used for **SPI only**. I think this sentence is not needed. Just to check, is Write-Status-Register used for non-spi? https://review.coreboot.org/c/flashrom/+/82908/comment/3a563c49_0e203384?us… : PS1, Line 110: : Write-Status-Register (WRSR) Handling : ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ : : ``FEATURE_WRSR_EWSR``, ``FEATURE_WRSR_WREN``, and ``FEATURE_WRSR_EITHER``. These bits used for **SPI only**. : : The Write Status Register (WRSR) is used to configure various settings within the flash chip, including write protection and : other features. The way WRSR is accessed varies between SPI flash chips, leading to the need for these feature bits. : : * ``FEATURE_WRSR_EWSR``: : This indicates that we need an **Enable-Write-Status-Register** (EWSR) instruction which opens the status register for the : immediately-followed next WRSR instruction. Usually, the opcode is **0x50**. : : * ``FEATURE_WRSR_WREN``: : This indicates that we need an **Write-Enable** (WREN) instruction to set the Write Enable Latch (WEL) bit. The WEL bit : must be set priort to every WRSR command. Usually, the opcode is **0x06**. : : * ``FEATURE_WRSR_EITHER``: : This indicates that either EWSR or WREN is supported in this chip. > Hi Anastasia: […] Thank you for explaining! It's really good that I know your future plans. The plan is good. I added few more comments, with your plan in mind. I would say, if a feature bit can be explain in 4 words, it can be inline comment in the flash.h. But in some cases, it's much better to have a more detailed few lines docs, and then it can go here. -- To view, visit https://review.coreboot.org/c/flashrom/+/82908?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I34c20933a375380c8702f79ac637595cd3466000 Gerrit-Change-Number: 82908 Gerrit-PatchSet: 1 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Sat, 15 Jun 2024 09:51:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hsuan-ting Chen <roccochen(a)google.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[L] Change in flashrom[main]: Add support for more XMC series
by Ssunk (Code Review) 15 Jun '24

15 Jun '24

Ssunk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83089?usp=email ) Change subject: Add support for more XMC series ...................................................................... Add support for more XMC series Add support for more XMC series Change-Id: I4e4eec6553407466b4b84969a806f046f6bddcbf Signed-off-by: Kankan Sun <ssunkkan(a)gmail.com> --- M flashchips.c M include/flashchips.h 2 files changed, 304 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/89/83089/1 diff --git a/flashchips.c b/flashchips.c index 86ebce3..471d73d 100644 --- a/flashchips.c +++ b/flashchips.c @@ -21864,17 +21864,17 @@ .name = "XM25QH80B", .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_M45PE80, + .model_id = XMC_XM25QH80B, .total_size = 1024, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, .tested = TEST_OK_PREW, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, .block_erasers = { { - .eraseblocks = { {4 * 1024, 256} }, + .eraseblocks = { {4 * 1024, 256 } }, .block_erase = SPI_BLOCK_ERASE_20, }, { .eraseblocks = { {32 * 1024, 32} }, @@ -21890,7 +21890,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP2_SRWD, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, .unlock = SPI_DISABLE_BLOCKPROTECT, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -21899,7 +21899,197 @@ { .vendor = "XMC", - .name = "XM25QH64C", + .name = "XM25QU80B", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QU80B, + .total_size = 1024, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256 } }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 32} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {1 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {1 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, + .unlock = SPI_DISABLE_BLOCKPROTECT, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {1650, 1950}, + }, + + { + .vendor = "XMC", + .name = "XM25QH16C/XM25QH16D", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QH16C, + .total_size = 2048, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, + .unlock = SPI_DISABLE_BLOCKPROTECT, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {2700, 3600}, + }, + + { + .vendor = "XMC", + .name = "XM25QU16C", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QU16C, + .total_size = 2048, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, + .unlock = SPI_DISABLE_BLOCKPROTECT, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {1650, 1950}, + }, + + { + .vendor = "XMC", + .name = "XM25QH32C/XM25QH32D", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QH32C, + .total_size = 4096, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, + .unlock = SPI_DISABLE_BLOCKPROTECT, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {2700, 3600}, + }, + + { + .vendor = "XMC", + .name = "XM25QU32C", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QU32C, + .total_size = 4096, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, + .unlock = SPI_DISABLE_BLOCKPROTECT, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {1650, 1950}, + }, + + { + .vendor = "XMC", + .name = "XM25QH64C/XM25QH64D", .bustype = BUS_SPI, .manufacture_id = ST_ID, .model_id = XMC_XM25QH64C, @@ -22023,7 +22213,7 @@ { .vendor = "XMC", - .name = "XM25QH128C", + .name = "XM25QH128C/XM25QH128D", .bustype = BUS_SPI, .manufacture_id = ST_ID, .model_id = XMC_XM25QH128C, @@ -22071,7 +22261,7 @@ { .vendor = "XMC", - .name = "XM25QU128C", + .name = "XM25QU128C/XM25QU128D", .bustype = BUS_SPI, .manufacture_id = ST_ID, .model_id = XMC_XM25QU128C, @@ -22111,7 +22301,7 @@ { .vendor = "XMC", - .name = "XM25QH256C", + .name = "XM25QH256C/XM25QH256D", .bustype = BUS_SPI, .manufacture_id = ST_ID, .model_id = XMC_XM25QH256C, @@ -22161,7 +22351,7 @@ { .vendor = "XMC", - .name = "XM25QU256C", + .name = "XM25QU256C/XM25QU256D", .bustype = BUS_SPI, .manufacture_id = ST_ID, .model_id = XMC_XM25QU256C, @@ -22203,6 +22393,102 @@ { .vendor = "XMC", + .name = "XM25QH512C/XM25QH512D", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QH512C, + .total_size = 64*1024, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN + | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = SPI_BLOCK_ERASE_21, + }, { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 2048} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_DC, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {64 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {64 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, /* TODO: improve */ + .unlock = SPI_DISABLE_BLOCKPROTECT, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {2700, 3600}, + }, + + { + .vendor = "XMC", + .name = "XM25QU512C/XM25QU512D", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QU512C, + .total_size = 64*1024, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN + | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = SPI_BLOCK_ERASE_21, + }, { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 2048} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_DC, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {64 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {64 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, /* TODO: improve */ + .unlock = SPI_DISABLE_BLOCKPROTECT, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {1650, 1950}, + }, + + { + .vendor = "XMC", .name = "XM25RU256C", .bustype = BUS_SPI, .manufacture_id = ST_ID, diff --git a/include/flashchips.h b/include/flashchips.h index 691ffc5..0666399 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -853,6 +853,15 @@ #define XMC_XM25QH256C 0x4019 #define XMC_XM25QU256C 0x4119 #define XMC_XM25RU256C 0x4419 +#define XMC_XM25QH80B 0x4014 +#define XMC_XM25QU80B 0x5014 +#define XMC_XM25QH16C 0x4015 /* Same as XM25QH16D */ +#define XMC_XM25QU16C 0x5015 +#define XMC_XM25QH32C 0x4016 /* Same as XM25QH32D */ +#define XMC_XM25QU32C 0x5016 +#define XMC_XM25QH64C 0x4017 /* Same as XM25QH64D */ +#define XMC_XM25QH512C 0x4020 /* Same as XM25QH512D */ +#define XMC_XM25QU512C 0x4120 /* Same as XM25QU512D */ #define ST_M25PX80 0x7114 #define ST_M25PX16 0x7115 #define ST_M25PX32 0x7116 -- To view, visit https://review.coreboot.org/c/flashrom/+/83089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I4e4eec6553407466b4b84969a806f046f6bddcbf Gerrit-Change-Number: 83089 Gerrit-PatchSet: 1 Gerrit-Owner: Ssunk <ssunkkan(a)gmail.com>

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[XS] Change in flashrom[main]: MAINTAINERS: Add Anastasia Klimchuk for CI script
by Peter Marheine (Code Review) 14 Jun '24

14 Jun '24

Attention is currently required from: Anastasia Klimchuk. Peter Marheine has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/83063?usp=email ) Change subject: MAINTAINERS: Add Anastasia Klimchuk for CI script ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/83063?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0aa30ffc69117e933e1bfbb07a456b1709693c59 Gerrit-Change-Number: 83063 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Fri, 14 Jun 2024 02:51:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in flashrom[main]: MAINTAINERS: Add Anastasia Klimchuk for CI script
by Anastasia Klimchuk (Code Review) 13 Jun '24

13 Jun '24

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83063?usp=email ) Change subject: MAINTAINERS: Add Anastasia Klimchuk for CI script ...................................................................... MAINTAINERS: Add Anastasia Klimchuk for CI script Change-Id: I0aa30ffc69117e933e1bfbb07a456b1709693c59 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M MAINTAINERS 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/63/83063/1 diff --git a/MAINTAINERS b/MAINTAINERS index f4e0c9a..a897a12 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -195,6 +195,11 @@ S: Maintained F: util/flashrom.bash-completion.tmpl +CONTINUOUS INTEGRATION SCRIPT +M: Anastasia Klimchuk <aklm(a)chromium.org> +S: Maintained +F: test_build.sh + FLASHROM TESTER M: Hsuan Ting Chen <roccochen(a)google.com> R: Evan Benn <evanbenn(a)gmail.com> -- To view, visit https://review.coreboot.org/c/flashrom/+/83063?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0aa30ffc69117e933e1bfbb07a456b1709693c59 Gerrit-Change-Number: 83063 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org>

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[XS] Change in flashrom[main]: flashchips: Add support for chip model GD25LB128E/GD25LR128E
by Anastasia Klimchuk (Code Review) 13 Jun '24

13 Jun '24

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Victor Lim. Anastasia Klimchuk has posted comments on this change by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/83012?usp=email ) Change subject: flashchips: Add support for chip model GD25LB128E/GD25LR128E ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/83012?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I8e8ad6bd69e2159b7cc2b64a7a8c7fcb1399294d Gerrit-Change-Number: 83012 Gerrit-PatchSet: 2 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Thu, 13 Jun 2024 02:26:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in flashrom[main]: flashchips: Add support for chip model GD25LB128E/GD25LR128E
by Victor Lim (Code Review) 13 Jun '24

13 Jun '24

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer. Victor Lim has posted comments on this change by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/83012?usp=email ) Change subject: flashchips: Add support for chip model GD25LB128E/GD25LR128E ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/83012/comment/c015a44c_08b74aeb?us… : PS1, Line 7: GD25LQ128E/GD25LB128E/GD25LR128E/GD25LQ128D/GD25LQ128C > You can replace this list with GD25LB128E/GD25LR128E , because you add two models, and the others we […] Done https://review.coreboot.org/c/flashrom/+/83012/comment/c3961701_0f048537?us… : PS1, Line 9: Adding GD25LQ128E/GD25LB128E/GD25LR128E/GD25LQ128D/GD25LQ128C to flashchip.c : : These part # sharing the same ID, form, fit, function, produced with different process node: 1.8V 128Mbit > You need to wrap the commit message to be 72 chars max width. […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/83012?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I8e8ad6bd69e2159b7cc2b64a7a8c7fcb1399294d Gerrit-Change-Number: 83012 Gerrit-PatchSet: 2 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Thu, 13 Jun 2024 01:35:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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