June 2024 - flashrom-gerrit - mail.coreboot.org

[S] Change in flashrom[main]: flashchips: add support for MX77U51250F chip
by Anastasia Klimchuk (Code Review) 21 Jun '24

21 Jun '24

Attention is currently required from: Bora Guvendik, DZ, Nikolai Artemiev, Stefan Reinauer. Anastasia Klimchuk has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/flashrom/+/82626?usp=email ) Change subject: flashchips: add support for MX77U51250F chip ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Daniel, is it possible to get the datasheet for MX77U51250F ? I would check the values in this patch. Or at least, maybe you or Bora could send it to me (but if there is a link, that would be perfect). Thank you so much! -- To view, visit https://review.coreboot.org/c/flashrom/+/82626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I2c2e94f01dc63f60cf636bc6afe1f033e2a6f83c Gerrit-Change-Number: 82626 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: DZ <danielzhang(a)mxic.com.cn> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: DZ <danielzhang(a)mxic.com.cn> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 21 Jun 2024 01:09:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in flashrom[main]: ich_descriptor: Fix chipset_names index for Intel Meteor Lake
by Hsuan-ting Chen (Code Review) 21 Jun '24

21 Jun '24

Attention is currently required from: Anastasia Klimchuk, Hsuan Ting Chen, Sam McNally, Subrata Banik. Hsuan-ting Chen has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/flashrom/+/83143?usp=email ) Change subject: ich_descriptor: Fix chipset_names index for Intel Meteor Lake ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/83143?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ic09cf0474c980369bcbf90924d45f697bc1b0a0d Gerrit-Change-Number: 83143 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Fri, 21 Jun 2024 00:48:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in flashrom[main]: flashchips: Set default wp test status for chips with custom config
by Sergii Dmytruk (Code Review) 20 Jun '24

20 Jun '24

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer. Sergii Dmytruk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/83132?usp=email ) Change subject: flashchips: Set default wp test status for chips with custom config ...................................................................... Patch Set 1: (2 comments) File flashchips.c: https://review.coreboot.org/c/flashrom/+/83132/comment/47f27c43_8f4b055e?us… : PS1, Line 2651: .tested = {.probe = NT, .read = NT, .erase = NT, .write = BAD, .wp = NT}, The chip seems to have only sector-based write protection and no block protection. "B" was chosen for block protection and sector protection is not implemented, so maybe this should be `NA`. https://review.coreboot.org/c/flashrom/+/83132/comment/1aac5416_5d07c594?us… : PS1, Line 3720: .tested = {.probe = OK, .read = OK, .erase = BAD, .write = BAD, .wp = NT}, It's [this chip](https://pdf1.alldatasheet.com/datasheet-pdf/view/57384/CATALYST/CAT28…, right? I see no write-protection in there. -- To view, visit https://review.coreboot.org/c/flashrom/+/83132?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I6ed8e04cd215865dc6a7d9415634dedbe3014ab5 Gerrit-Change-Number: 83132 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Thu, 20 Jun 2024 21:37:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in flashrom[main]: print.c: Print B (block-protect) test status of the chips
by Sergii Dmytruk (Code Review) 20 Jun '24

20 Jun '24

Attention is currently required from: Anastasia Klimchuk. Sergii Dmytruk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/83131?usp=email ) Change subject: print.c: Print B (block-protect) test status of the chips ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/83131?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: If697fe3ba93dbe34bb8f7a9a4b1686fdb8b3ee58 Gerrit-Change-Number: 83131 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 20 Jun 2024 21:20:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in flashrom[main]: ichspi: Add support for Panther Lake
by Subrata Banik (Code Review) 20 Jun '24

20 Jun '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83144?usp=email ) Change subject: ichspi: Add support for Panther Lake ...................................................................... ichspi: Add support for Panther Lake This patch adds Panther Lake support into flashrom. BUG=b:347669091 TEST=Flashrom is able to detect PTL SPI DID and show chipset name as below: > flashrom --flash-name .... Found chipset "Intel Panther Lake-U/H 12Xe". .... > flashrom - internal --ifd -i fd -i bios -r /tmp/bios.rom .... Reading ich_descriptor... done. Assuming chipset 'Panther Lake'. Using regions: "bios", "fd". Reading flash... done. SUCCESS Change-Id: I99cd8eb7cbb11381f8e8455b06cf90b9db77d8f0 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M chipset_enable.c M ich_descriptors.c M ichspi.c M include/programmer.h M util/ich_descriptors_tool/ich_descriptors_tool.c 5 files changed, 35 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/44/83144/1 diff --git a/chipset_enable.c b/chipset_enable.c index 1c24b92..facf29e 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -607,6 +607,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_ELKHART_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: @@ -715,6 +716,7 @@ case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_C740_SERIES_EMMITSBURG: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: boot_straps = boot_straps_pch500; break; case CHIPSET_APOLLO_LAKE: @@ -750,6 +752,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: @@ -1019,6 +1022,11 @@ return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_METEOR_LAKE); } +static int enable_flash_ptl(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_PANTHER_LAKE); +} + static int enable_flash_mcc(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) { return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_ELKHART_LAKE); @@ -2186,6 +2194,8 @@ {0x8086, 0x7a8d, B_S, NT, "Intel", "WM690", enable_flash_pch600}, {0x8086, 0x7a8c, B_S, NT, "Intel", "HM670", enable_flash_pch600}, {0x8086, 0x7e23, B_S, DEP, "Intel", "Meteor Lake-P/M", enable_flash_mtl}, + {0x8086, 0xe323, B_S, DEP, "Intel", "Panther Lake-U/H 12Xe", enable_flash_ptl}, + {0x8086, 0xe423, B_S, DEP, "Intel", "Panther Lake-H 4Xe", enable_flash_ptl}, #endif {0}, }; diff --git a/ich_descriptors.c b/ich_descriptors.c index 6de4316..ce611bb 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -50,6 +50,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_ELKHART_LAKE: case CHIPSET_JASPER_LAKE: return 16; @@ -80,6 +81,7 @@ case CHIPSET_APOLLO_LAKE: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: @@ -122,7 +124,7 @@ "C620 series Lewisburg", "C740 series Emmitsburg", "300 series Cannon Point", "400 series Comet Point", "500 series Tiger Point", "600 series Alder Point", "Apollo Lake", "Gemini Lake", "Jasper Lake", "Elkhart Lake", - "Meteor Lake", + "Meteor Lake", "Panther Lake", }; if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names)) cs = 0; @@ -220,6 +222,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: @@ -319,6 +322,7 @@ case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_C740_SERIES_EMMITSBURG: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: return freq_str[3][value]; case CHIPSET_ELKHART_LAKE: return freq_str[4][value]; @@ -368,6 +372,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: @@ -508,7 +513,9 @@ cs == CHIPSET_500_SERIES_TIGER_POINT || cs == CHIPSET_600_SERIES_ALDER_POINT || cs == CHIPSET_C740_SERIES_EMMITSBURG || - cs == CHIPSET_JASPER_LAKE || cs == CHIPSET_METEOR_LAKE) { + cs == CHIPSET_JASPER_LAKE || + cs == CHIPSET_METEOR_LAKE || + cs == CHIPSET_PANTHER_LAKE) { const char *const master_names[] = { "BIOS", "ME", "GbE", "DevE", "EC", }; @@ -1083,6 +1090,8 @@ return CHIPSET_JASPER_LAKE; else if (content->CSSO == 0x70) return CHIPSET_METEOR_LAKE; + else if (content->CSSO == 0x60) + return CHIPSET_PANTHER_LAKE; } msg_pwarn("Unknown flash descriptor, assuming 500 series compatibility.\n"); return CHIPSET_500_SERIES_TIGER_POINT; @@ -1107,6 +1116,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: @@ -1268,6 +1278,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: @@ -1314,6 +1325,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: diff --git a/ichspi.c b/ichspi.c index cc56e0c..f74fb05 100644 --- a/ichspi.c +++ b/ichspi.c @@ -2111,6 +2111,7 @@ case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: *num_pr = 6; /* Includes GPR0 */ *reg_pr0 = PCH100_REG_FPR0; swseq->reg_ssfsc = PCH100_REG_SSFSC; @@ -2151,6 +2152,7 @@ case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: *num_freg = 16; break; default: @@ -2213,6 +2215,7 @@ case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: tmp = mmio_readl(spibar + PCH100_REG_DLOCK); msg_pdbg("0x0c: 0x%08"PRIx32" (DLOCK)\n", tmp); prettyprint_pch100_reg_dlock(tmp); @@ -2294,6 +2297,7 @@ case CHIPSET_BAYTRAIL: case CHIPSET_ELKHART_LAKE: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: break; default: ichspi_bbar = mmio_readl(spibar + ICH9_REG_BBAR); @@ -2333,6 +2337,7 @@ case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: case CHIPSET_METEOR_LAKE: + case CHIPSET_PANTHER_LAKE: break; default: tmp = mmio_readl(spibar + ICH9_REG_FPB); @@ -2376,8 +2381,9 @@ ich_gen == CHIPSET_GEMINI_LAKE || ich_gen == CHIPSET_JASPER_LAKE || ich_gen == CHIPSET_ELKHART_LAKE || - ich_gen == CHIPSET_METEOR_LAKE)) { - msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Jasper/Elkhart/Meteor Lake.\n"); + ich_gen == CHIPSET_METEOR_LAKE || + ich_gen == CHIPSET_PANTHER_LAKE)) { + msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Jasper/Elkhart/Meteor/Panther Lake.\n"); ich_spi_mode = ich_hwseq; } diff --git a/include/programmer.h b/include/programmer.h index 8ef6ffd..a90624b 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -363,6 +363,7 @@ CHIPSET_ELKHART_LAKE, /* All chipsets after METEOR_LAKE should support checking BIOS_BM to get read/write access to of FREG0~15 */ CHIPSET_METEOR_LAKE, + CHIPSET_PANTHER_LAKE, }; /* ichspi.c */ diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 844d8e9..4cdf798 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -248,6 +248,8 @@ cs = CHIPSET_ELKHART_LAKE; else if (strcmp(csn, "meteor") == 0) cs = CHIPSET_METEOR_LAKE; + else if (strcmp(csn, "panther") == 0) + cs = CHIPSET_PANTHER_LAKE; } ret = read_ich_descriptors_from_dump(buf, len, &cs, &desc); -- To view, visit https://review.coreboot.org/c/flashrom/+/83144?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I99cd8eb7cbb11381f8e8455b06cf90b9db77d8f0 Gerrit-Change-Number: 83144 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in flashrom[main]: ich_descriptor: Fix chipset_names index for Intel Meteor Lake
by Subrata Banik (Code Review) 20 Jun '24

20 Jun '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83143?usp=email ) Change subject: ich_descriptor: Fix chipset_names index for Intel Meteor Lake ...................................................................... ich_descriptor: Fix chipset_names index for Intel Meteor Lake commit hash 85b977151b8f57 (ichspi.c: Add support for region 9 and beyond in Meteor Lake) moved the Intel Meteor Lake macro in programmer.h, causing flashrom to display an incorrect chipset name for Meteor Lake platforms. This patch updates the corresponding chipset_names index to resolve this issue. TEST=Verified correct chipset name in flashrom output for Meteor Lake chipset (google/rex0 board). Change-Id: Ic09cf0474c980369bcbf90924d45f697bc1b0a0d Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M ich_descriptors.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/43/83143/1 diff --git a/ich_descriptors.c b/ich_descriptors.c index b11a78d..6de4316 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -121,7 +121,8 @@ "9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point", "C620 series Lewisburg", "C740 series Emmitsburg", "300 series Cannon Point", "400 series Comet Point", "500 series Tiger Point", "600 series Alder Point", - "Meteor Lake", "Apollo Lake", "Gemini Lake", "Jasper Lake", "Elkhart Lake", + "Apollo Lake", "Gemini Lake", "Jasper Lake", "Elkhart Lake", + "Meteor Lake", }; if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names)) cs = 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/83143?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ic09cf0474c980369bcbf90924d45f697bc1b0a0d Gerrit-Change-Number: 83143 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in flashrom[main]: flashchips: add GD25LB256E chip model
by Victor Lim (Code Review) 20 Jun '24

20 Jun '24

Victor Lim has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83140?usp=email ) Change subject: flashchips: add GD25LB256E chip model ...................................................................... flashchips: add GD25LB256E chip model adding GD25LB256E to the model GD25LR256E which share the same feature. The datasheet link https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-0… Change-Id: I0aa520b068a86098f6b4a1b68401c425b33e501f Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- M flashchips.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/40/83140/1 diff --git a/flashchips.c b/flashchips.c index 10071fd..1dba182 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6899,14 +6899,14 @@ { .vendor = "GigaDevice", - .name = "GD25LR256E", + .name = "GD25LB256E/GD25LR256E", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25LR256E, .total_size = 32768, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_4BA, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PREWB, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, .block_erasers = -- To view, visit https://review.coreboot.org/c/flashrom/+/83140?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I0aa520b068a86098f6b4a1b68401c425b33e501f Gerrit-Change-Number: 83140 Gerrit-PatchSet: 1 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com>

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[S] Change in flashrom[main]: doc: Add current numbers of supported devices to the intro page
by Peter Marheine (Code Review) 19 Jun '24

19 Jun '24

Attention is currently required from: Anastasia Klimchuk. Peter Marheine has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/83130?usp=email ) Change subject: doc: Add current numbers of supported devices to the intro page ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/83130?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I7531521955dcf01348ed2ba9c54316b32b9cd925 Gerrit-Change-Number: 83130 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Wed, 19 Jun 2024 23:27:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in flashrom[main]: print.c: Print total numbers of supported USB and PCI devices
by Peter Marheine (Code Review) 19 Jun '24

19 Jun '24

Attention is currently required from: Anastasia Klimchuk. Peter Marheine has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/83129?usp=email ) Change subject: print.c: Print total numbers of supported USB and PCI devices ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/83129?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ie011db3985172d05f5160d1cb1cc39a4422a5750 Gerrit-Change-Number: 83129 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Wed, 19 Jun 2024 23:24:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in flashrom[main]: hwaccess_x86_io: Fix Android compilation with bionic libc
by Jakub Czapiga (Code Review) 19 Jun '24

19 Jun '24

Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83133?usp=email ) Change subject: hwaccess_x86_io: Fix Android compilation with bionic libc ...................................................................... hwaccess_x86_io: Fix Android compilation with bionic libc Recently Android Bionic LibC got sys/io.h. Use this header to access ioperm(). Use Assembly for I/O, as Bionic does not have inb(), outb(), etc. Change-Id: Id80b83c2718679c925ed6ddfe33cbe837eea0429 Signed-off-by: Jakub Czapiga <czapiga(a)google.com> --- M hwaccess_x86_io.c 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/33/83133/1 diff --git a/hwaccess_x86_io.c b/hwaccess_x86_io.c index 93d29d8..70b7439 100644 --- a/hwaccess_x86_io.c +++ b/hwaccess_x86_io.c @@ -58,10 +58,11 @@ #define USE_IOPERM 9 #if defined(__ANDROID__) -#include <sys/glibc-syscalls.h> +#include <sys/io.h> +#include <unistd.h> -#define IO_PORT_PERMISSION USE_IOPL -#define IO_PORT_FUNCTION USE_LIBC_TARGET_LAST +#define IO_PORT_PERMISSION USE_IOPERM +#define IO_PORT_FUNCTION USE_ASM #endif #if defined(__linux__) && !defined(__ANDROID__) -- To view, visit https://review.coreboot.org/c/flashrom/+/83133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Id80b83c2718679c925ed6ddfe33cbe837eea0429 Gerrit-Change-Number: 83133 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <czapiga(a)google.com>

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