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Change subject: flashchips: Add support for MXIC MX25R8035F
......................................................................
Patch Set 1: Code-Review+2
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Change subject: ich: Add names for region 5, 9, 10, 11, 12, 15
......................................................................
Patch Set 7: Code-Review+2
(1 comment)
File util/ich_descriptors_tool/ich_descriptors_tool.c:
https://review.coreboot.org/c/flashrom/+/81356/comment/2503b8cf_7912b258 :
PS5, Line 42: 10GbE0
> The OpROM is located on 10GbE#2, not 10GbE#1. While I considered changing the output to:
Region 12 (10GbE1/OpROM) is unused.
...this would require significant code modifications due to padding width adjustments. I've decided to postpone this change for now.
Yes, my typo, it would be in the place of 10GbE2 !
I think your idea is very good, to update region name as 10GbE2/OpROM (since it's used in a generic way), but certainly it goes outside the scope of the patch. If you decide to do this later, you will, of course, be very welcome!
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Change subject: ich: Add names for region 5, 9, 10, 11, 12, 15
......................................................................
Patch Set 7:
(1 comment)
File util/ich_descriptors_tool/ich_descriptors_tool.c:
https://review.coreboot.org/c/flashrom/+/81356/comment/910f6bd8_7f65b6da :
PS5, Line 42: 10GbE0
Currently it looks like:
```
--- Details ---
Region 0 (Descr. ) 0x00000000 - 0x00000000
Region 1 (BIOS ) 0x00000000 - 0x00000000
Region 2 (ME ) 0x00000000 - 0x00000000
Region 3 (GbE ) is unused.
Region 4 (Platf. ) is unused.
Region 5 (DevExp ) is unused.
Region 6 (BIOS2 ) is unused.
Region 7 (unknown) is unused.
Region 8 (EC/BMC ) is unused.
Region 9 (unknown) 0x00000000 - 0x00000000
Region 10 (IE ) is unused.
Region 11 (10GbE0 ) is unused.
Region 12 (10GbE1 ) is unused.
Region 13 (unknown) is unused.
Region 14 (unknown) is unused.
Region 15 (PTT ) is unused.
=== Master Section ===
FLMSTR1 0x00000000
FLMSTR2 0x00000000
```
> Is it true then, that for C620 the tool will print 10GbE1 instead of OpROM ?
The OpROM is located on 10GbE#2, not 10GbE#1. While I considered changing the output to:
`Region 12 (10GbE1/OpROM) is unused.`
...this would require significant code modifications due to padding width adjustments. I've decided to postpone this change for now.
> I just want to fully understand.
Absolutely! This is a complex area with some documentation being confidential. I've definitely gained insights while working on this CL.
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Change subject: ich: Add names for region 5, 9, 10, 11, 12, 15
......................................................................
Patch Set 7:
(1 comment)
File util/ich_descriptors_tool/ich_descriptors_tool.c:
https://review.coreboot.org/c/flashrom/+/81356/comment/ce5005a7_d90ecdd3 :
PS5, Line 42: 10GbE0
> I could only find 2: […]
Thanks so much for your explanation! So the region names can be slightly different from one chipset to another.
But `util/ich_descriptors_tool/ich_descriptors_tool.c` have only one list of region names.
Is it true then, that for C620 the tool will print `10GbE1` instead of `OpROM` ?
I know the tool was like this before, and coreboot code that you linked seems to have one list of region names. I don't think you need to change the tool for the patch, I just want to fully understand.
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Change subject: udelay: only use OS time for delays, except on DOS
......................................................................
Patch Set 9: Code-Review+2
(1 comment)
Patchset:
PS9:
Peter, I think you can wait for let's say another week, in case someone else wants to have a look, and then resolve this comment and submit (if no more comments come up).
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Change subject: ich: Add names for region 5, 9, 10, 11, 12, 15
......................................................................
Patch Set 7:
(3 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/81356/comment/e7537cce_2bc11460 :
PS1, Line 12: * Incorporate missing region names from https://github.com/coreboot/coreboot/blob/main/util/ifdtool/ifdtool.c for completeness.
> Just wanted to follow up on this, since the patch is waiting for a while. […]
Unfortunately, I don't have specific knowledge about 'flash descriptor V2' to help with this.
These patches were tested on MTL (Core Ultra) to ensure Region 9 access. We verified this through local testing, and the `flashrom -VV` command correctly displayed BIOS read/write access permissions for Region 9, which is critical to MTL.
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/81356/comment/53cc33b4_9cf166e1 :
PS7, Line 558: 10GbE
FYR: C620
File util/ich_descriptors_tool/ich_descriptors_tool.c:
https://review.coreboot.org/c/flashrom/+/81356/comment/a3f2bab4_853ae67c :
PS5, Line 42: 10GbE0
> This one occurrence that I noticed when the new name is different from the old one. […]
I could only find 2:
1. The one in ich_descriptors.c#442: This table seems to be a summary table, so only include the most frequently occurring names. (Update with 10GbE0, 10GbE1)
2. The one in ichspi.c#558: This table is for Intel C620. See https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/c62… datasheet page 1904, they only have one 10GbE and they have OPROM (option ROM)
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Hello Anastasia Klimchuk, Hsuan Ting Chen, Stefan Reinauer, Subrata Banik, build bot (Jenkins),
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Code-Review+1 by Subrata Banik, Verified+1 by build bot (Jenkins)
Change subject: ich: Add names for region 5, 9, 10, 11, 12, 15
......................................................................
ich: Add names for region 5, 9, 10, 11, 12, 15
Add Region 9 for Intel Meteor Lake; update missing regions.
* Include Region 9 as officially required for Intel Meteor Lake platform.
* Incorporate missing region names from https://github.com/coreboot/coreboot/blob/main/util/ifdtool/ifdtool.c for completeness.
Region 5: Device Expansion (DE or DevExp)
Region 9: Device Expansion 2 (DE2 or DevExp2)
Region 10: Innovation Engine (IE)
Region 11: 10 GbE 0
Region 12: 10 GbE 1
Region 15: PTT
BUG=b:319773700
TEST=Run `flashrom -VV` on MTL and see all the regions are printed out
Change-Id: I3b164ce4ae84bfd523fcd8be416c5d13183ed632
Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org>
---
M ich_descriptors.c
M ichspi.c
M util/ich_descriptors_tool/ich_descriptors_tool.c
3 files changed, 10 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/56/81356/7
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Change subject: udelay: only use OS time for delays, except on DOS
......................................................................
Patch Set 9:
(1 comment)
File tests/udelay.c:
https://review.coreboot.org/c/flashrom/+/81545/comment/2a8e63e9_626a9928 :
PS9, Line 41: This test could fail spuriously on a heavily-loaded system
> Brian, you have good points. Thank you for sharing your valuable experience! […]
We'd have to write the test differently to handle a potential infinite loop, since the test only checks elapsed time once the delay function returns. I think we'll leave it as-is for now, and consider adjustment later if it seems too flaky.
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Change subject: flashchips: Split and add write-protect support for MX25L12833F
......................................................................
flashchips: Split and add write-protect support for MX25L12833F
MX25L12833F datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/8934/MX25L12833F,%203V…
Status register: page 30 table 7 (BP0~BP3, SRWD)
Configuration register: page 31 table 8 (TB)
Security register: page 57 table 12 (WPSEL)
MX25L12835F datasheet:
https://www.macronix.com/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V…
Status register: page 31(BP0~BP3, SRWD)
Configuration register: page 32 table 7 (TB)
Security register: page 61 table 9 (WPSEL)
MX25L12845E datasheet: (no CONFIG)
https://www.mxic.com.tw/Lists/Datasheet/Attachments/8693/MX25L12845E,%203V,…
Status register: page 17 (BP0~BP3, SRWD)
Security register: page 29 (WPSEL)
MX25L12865E datasheet: (no CONFIG)
https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L6465E,_MX25L12865…
Status register: page 19 (BP0~BP3, SRWD)
Security register: page 31 (WPSEL)
MX25L12873F datasheet: (no hardware WP)
https://www.mxic.com.tw/Lists/Datasheet/Attachments/8652/MX25L12873F,%203V,…
Status register: page 31(BP0~BP3, SRWD)
Configuration register: page 32 table 7 (TB)
Security register: page 60 table 9 (WPSEL)
Splits the MX25L12833F/MX25L12835F/MX25L12845E/MX25L12865E/MX25L12873F
group into three subgroups:
* MX25L12833F: This chip have the configuration register and WP tested
* MX25L12835F/MX25L12873F: These chips have the configuration register.
* MX25L12845E/MX25L12865E: These chips don't have the configuration
register.
Tests the write protect functionality on the MX25L12833F chip only.
BUG=b:332486637
TEST=Test flashrom --wp-disable with MX25L12833FZNI-10 on ChromeOS
Change-Id: I379c833eea3ed3487504126f45c6df672a772ddc
Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org>
---
M flashchips.c
1 file changed, 104 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/92/81792/4
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