April 2024 - flashrom-gerrit - mail.coreboot.org

[XS] Change in flashrom[main]: flashrom: Don't throw around "delay 1 second" so lightly
by Brian Norris (Code Review) 22 Apr '24

22 Apr '24

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Peter Marheine. Brian Norris has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/80807?usp=email ) Change subject: flashrom: Don't throw around "delay 1 second" so lightly ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > > If nobody knows why this is necessary or how to reproduce, I think it's okay to remove. […] Unfortunately, this hack survived so long it migrated from the CLI to the library. So a CLI flag won't really provide an escape hatch for all users -- unless you also want to also add a libflashrom flag for it?? I'm still somewhat of a lazy opinion here: 1. I doubt that anything will come of either this CL, nor of a CLI flag that provides a bug-report-escape-hatch for it and 2. the whole `--verify` sequence is trivial enough to emulate on one's own [1]. That gets slightly more complex to implement if people are using environments without basic stuff like a decent shell or tools like `cmp`, or if they're using surgical flags (like `--include`). But it's not that hard. And the good news is we don't have to try #2 if I'm right about #1 😊 But if you still think we need a flag, I can give it a shot. And either way, do you want me to start such a mailing list thread, or were you suggesting I do this? [1] e.g., `flashrom --read /tmp/foo.bin`; `flashrom --write /my/new/image.bin --noverify`; `sleep 1`; `flashrom --read /tmp/bar.bin`; `cmp /tmp/foo.bin /tmp/bar.bin` -- To view, visit https://review.coreboot.org/c/flashrom/+/80807?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ie09651fede3f9f03425244c94a2da8bae00315fc Gerrit-Change-Number: 80807 Gerrit-PatchSet: 3 Gerrit-Owner: Brian Norris <briannorris(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Tue, 23 Apr 2024 00:23:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Brian Norris <briannorris(a)chromium.org> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Nikolai Artemiev <nartemiev(a)google.com> Comment-In-Reply-To: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: comment

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[XS] Change in flashrom[main]: flashrom: Don't throw around "delay 1 second" so lightly
by Anastasia Klimchuk (Code Review) 22 Apr '24

22 Apr '24

Attention is currently required from: Brian Norris, Nikolai Artemiev, Peter Marheine. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/80807?usp=email ) Change subject: flashrom: Don't throw around "delay 1 second" so lightly ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > If nobody knows why this is necessary or how to reproduce, I think it's okay to remove. Yes, true. I was trying to find out which exactly chips needed that extra delay, but no success so far. If we knew which chips we could add a feature flag as Nikolai suggested, and mark them in flashchips. But it seems, we don't know. So your plan looks very reasonable: an option will cover for the edge cases (if they exist). I was thinking to start from a post on a mailing list, very specifically about removing 1s delay (there has been none dedicated thread), so that if someone suddenly recalls information about those odd chips, they can share. Even if no one responds, it stays in archives as a record of decision being made with explanation why. And then update this patch with an option, post link to patch to the thread. That should be enough for the "paperwork" :) -- To view, visit https://review.coreboot.org/c/flashrom/+/80807?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ie09651fede3f9f03425244c94a2da8bae00315fc Gerrit-Change-Number: 80807 Gerrit-PatchSet: 3 Gerrit-Owner: Brian Norris <briannorris(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Attention: Brian Norris <briannorris(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Mon, 22 Apr 2024 11:03:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Brian Norris <briannorris(a)chromium.org> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Nikolai Artemiev <nartemiev(a)google.com> Comment-In-Reply-To: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: comment

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[L] Change in flashrom[main]: <Flashrom SPI NOR>: adding a few new SPI NOR part numbers
by Anastasia Klimchuk (Code Review) 22 Apr '24

22 Apr '24

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Victor Lim. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/81970?usp=email ) Change subject: <Flashrom SPI NOR>: adding a few new SPI NOR part numbers ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Victor, this is amazing, thank you so much for adding and updating so many chips! What you need to do now, is to split this large patch into several smaller ones. I can see some of the models are related and can be grouped together. So for example, GD25LB128E, GD25LQ128E, GD25LR128E can be in one patch. And then GD25LB256F, GD25LQ256H, GD25LR256F can be in the next patch, and so on. When you split your git commit locally, you will have a chain of commits in your local branch. And then when you push the whole chain to Gerrit, you will see all the patches in a chain as well. For commit titles, you can use the pattern: `flashchips: Add (or update) chip models <list models>` Another thing is, you need to provide links to public datasheets for the models added or updated in each patch. Thanks! -- To view, visit https://review.coreboot.org/c/flashrom/+/81970?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I1526eed830845d5391ca14c7fd3ac58a5aee71f2 Gerrit-Change-Number: 81970 Gerrit-PatchSet: 1 Gerrit-Owner: Victor Lim <victorswlim(a)yahoo.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <victorswlim(a)yahoo.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Mon, 22 Apr 2024 10:42:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in flashrom[main]: flashchips: Split and add write-protect support for MX25L12833F
by Anastasia Klimchuk (Code Review) 22 Apr '24

22 Apr '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/81792?usp=email ) Change subject: flashchips: Split and add write-protect support for MX25L12833F ...................................................................... flashchips: Split and add write-protect support for MX25L12833F MX25L12833F datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/8934/MX25L12833F,%203V… Status register: page 30 table 7 (BP0~BP3, SRWD) Configuration register: page 31 table 8 (TB) Security register: page 57 table 12 (WPSEL) MX25L12835F datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V… Status register: page 31(BP0~BP3, SRWD) Configuration register: page 32 table 7 (TB) Security register: page 61 table 9 (WPSEL) MX25L12845E datasheet: (no CONFIG) https://www.mxic.com.tw/Lists/Datasheet/Attachments/8693/MX25L12845E,%203V,… Status register: page 17 (BP0~BP3, SRWD) Security register: page 29 (WPSEL) MX25L12865E datasheet: (no CONFIG) https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L6465E,_MX25L12865… Status register: page 19 (BP0~BP3, SRWD) Security register: page 31 (WPSEL) MX25L12873F datasheet: (no hardware WP) https://www.mxic.com.tw/Lists/Datasheet/Attachments/8652/MX25L12873F,%203V,… Status register: page 31(BP0~BP3, SRWD) Configuration register: page 32 table 7 (TB) Security register: page 60 table 9 (WPSEL) Splits the MX25L12833F/MX25L12835F/MX25L12845E/MX25L12865E/MX25L12873F group into three subgroups: * MX25L12833F: This chip have the configuration register and WP tested * MX25L12835F/MX25L12873F: These chips have the configuration register. * MX25L12845E/MX25L12865E: These chips don't have the configuration register. Tests the write protect functionality on the MX25L12833F chip only. BUG=b:332486637 TEST=Test flashrom --wp-disable with MX25L12833FZNI-10 on ChromeOS Change-Id: I379c833eea3ed3487504126f45c6df672a772ddc Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/81792 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashchips.c 1 file changed, 103 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index 022b18a..373f28c 100644 --- a/flashchips.c +++ b/flashchips.c @@ -9005,13 +9005,60 @@ { .vendor = "Macronix", - .name = "MX25L12833F/MX25L12835F/MX25L12845E/MX25L12865E/MX25L12873F", + .name = "MX25L12833F", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L12805D, .total_size = 16384, .page_size = 256, - /* OTP: MX25L12833F has 1KB total, others have 512B total; enter 0xB1, exit 0xC1 */ + /* OTP: 1KB total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREWB, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6 is quad enable */ + .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {CONFIG, 3, OTP}, + .wps = {SECURITY, 7, OTP}, /* This bit is set by WPSEL command */ + }, + .decode_range = DECODE_RANGE_SPI25, + }, + + { + .vendor = "Macronix", + .name = "MX25L12835F/MX25L12873F", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L12805D, + .total_size = 16384, + .page_size = 256, + /* OTP: 512B total; enter 0xB1, exit 0xC1 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = PROBE_SPI_RDID, @@ -9035,12 +9082,65 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - /* TODO: security register and SBLK/SBULK; MX25L12835F: configuration register */ .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6 is quad enable */ .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {CONFIG, 3, OTP}, + .wps = {SECURITY, 7, OTP}, /* This bit is set by WPSEL command */ + }, + .decode_range = DECODE_RANGE_SPI25, + }, + + { + .vendor = "Macronix", + .name = "MX25L12845E/MX25L12865E", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L12805D, + .total_size = 16384, + .page_size = 256, + /* OTP: 512B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6 is quad enable */ + .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .wps = {SECURITY, 7, OTP}, /* This bit is set by WPSEL command */ + }, + .decode_range = DECODE_RANGE_SPI25, }, { -- To view, visit https://review.coreboot.org/c/flashrom/+/81792?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I379c833eea3ed3487504126f45c6df672a772ddc Gerrit-Change-Number: 81792 Gerrit-PatchSet: 7 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: DZ <danielzhang(a)mxic.com.cn> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-MessageType: merged

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[S] Change in flashrom[main]: flashchips: Add write protect function support for MX25R1635F
by Anastasia Klimchuk (Code Review) 22 Apr '24

22 Apr '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/81840?usp=email ) Change subject: flashchips: Add write protect function support for MX25R1635F ...................................................................... flashchips: Add write protect function support for MX25R1635F The MX25R1635F has been tested by ch341a programmer : read, write, erase and wp. We have tested --wp-enable, --wp-disable, --wp-list and --wp-range commands for write-protect feature. MX25R1635F datasheet is available at the following URL: https://www.macronix.com/Lists/Datasheet/Attachments/8702/MX25R1635F,%20Wid… Change-Id: I6e2b417ab177039618069d8e35132ddbfb814f03 Signed-off-by: DanielZhang <danielzhang(a)mxic.com.cn> Reviewed-on: https://review.coreboot.org/c/flashrom/+/81840 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashchips.c 1 file changed, 10 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index e1e774c..022b18a 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10103,8 +10103,8 @@ .total_size = 2048, .page_size = 256, /* OTP: 1024B total; enter 0xB1, exit 0xC1 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_OK_PREW, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_CFGR, + .tested = TEST_OK_PREWB, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, .block_erasers = @@ -10131,6 +10131,14 @@ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {CONFIG, 3, OTP} + }, + + .decode_range = DECODE_RANGE_SPI25, }, { -- To view, visit https://review.coreboot.org/c/flashrom/+/81840?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I6e2b417ab177039618069d8e35132ddbfb814f03 Gerrit-Change-Number: 81840 Gerrit-PatchSet: 2 Gerrit-Owner: DZ <danielzhang(a)mxic.com.cn> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in flashrom[main]: flashchips: Add support for MXIC MX25R8035F
by Anastasia Klimchuk (Code Review) 22 Apr '24

22 Apr '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/81837?usp=email ) Change subject: flashchips: Add support for MXIC MX25R8035F ...................................................................... flashchips: Add support for MXIC MX25R8035F The MX25R8035F has been tested by ch341a programmer : read, write, erase and wp. We have tested --wp-enable, --wp-disable, --wp-list and --wp-range commands for write-protect feature. MX25R8035F datasheet is available at the following URL: https://www.macronix.com/Lists/Datasheet/Attachments/8749/MX25R8035F,%20Wid… Change-Id: Iec244ffc29278c1f8c3ae47d17af2c4fe5fbe498 Signed-off-by: DanielZhang <danielzhang(a)mxic.com.cn> Reviewed-on: https://review.coreboot.org/c/flashrom/+/81837 Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M flashchips.c M include/flashchips.h 2 files changed, 48 insertions(+), 0 deletions(-) Approvals: Anastasia Klimchuk: Looks good to me, approved build bot (Jenkins): Verified diff --git a/flashchips.c b/flashchips.c index 7a40f07..e1e774c 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10213,6 +10213,53 @@ { .vendor = "Macronix", + .name = "MX25R8035F", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25R8035F, + .total_size = 1024, + .page_size = 256, + /* OTP: 1024B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_CFGR, + .tested = TEST_OK_PREWB, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 32} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {1 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {1 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit 6 is quad enable */ + .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1650, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {CONFIG, 3, OTP} + }, + + .decode_range = DECODE_RANGE_SPI25, + }, + + { + .vendor = "Macronix", .name = "MX25V4035F", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, diff --git a/include/flashchips.h b/include/flashchips.h index 103e6ea..c9303d5 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -540,6 +540,7 @@ #define MACRONIX_MX25R1635F 0x2815 #define MACRONIX_MX25R3235F 0x2816 #define MACRONIX_MX25R6435F 0x2817 +#define MACRONIX_MX25R8035F 0x2814 #define MACRONIX_MX29F001B 0x19 #define MACRONIX_MX29F001T 0x18 -- To view, visit https://review.coreboot.org/c/flashrom/+/81837?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Iec244ffc29278c1f8c3ae47d17af2c4fe5fbe498 Gerrit-Change-Number: 81837 Gerrit-PatchSet: 2 Gerrit-Owner: DZ <danielzhang(a)mxic.com.cn> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in flashrom[main]: flashrom: Don't throw around "delay 1 second" so lightly
by Peter Marheine (Code Review) 21 Apr '24

21 Apr '24

Attention is currently required from: Anastasia Klimchuk, Brian Norris, Nikolai Artemiev. Peter Marheine has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/80807?usp=email ) Change subject: flashrom: Don't throw around "delay 1 second" so lightly ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > My main concern is that there may be some chips in the flashchips database which need this delay, bu […] If nobody knows why this is necessary or how to reproduce, I think it's okay to remove. If we're feeling particularly conservative, we could add an option (perhaps `--extra-readback-delay`, but feel free to bikeshed the name) that enables the extra delay so there's an escape hatch available if it turns out somebody has such a chip- then we can suggest using that option as a fallback in `emergency_help_message()` and ask that people report cases where they need to use it (so hopefully over time the escape hatch would become unnecessary). -- To view, visit https://review.coreboot.org/c/flashrom/+/80807?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ie09651fede3f9f03425244c94a2da8bae00315fc Gerrit-Change-Number: 80807 Gerrit-PatchSet: 3 Gerrit-Owner: Brian Norris <briannorris(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Attention: Brian Norris <briannorris(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Mon, 22 Apr 2024 00:50:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Brian Norris <briannorris(a)chromium.org> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: comment

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[S] Change in flashrom[main]: ich: Add names for region 5, 9, 10, 11, 12, 15
by Anastasia Klimchuk (Code Review) 21 Apr '24

21 Apr '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/81356?usp=email ) Change subject: ich: Add names for region 5, 9, 10, 11, 12, 15 ...................................................................... ich: Add names for region 5, 9, 10, 11, 12, 15 Add Region 9 for Intel Meteor Lake; update missing regions. * Include Region 9 as officially required for Intel Meteor Lake platform. * Incorporate missing region names from https://github.com/coreboot/coreboot/blob/main/util/ifdtool/ifdtool.c for completeness. Region 5: Device Expansion (DE or DevExp) Region 9: Device Expansion 2 (DE2 or DevExp2) Region 10: Innovation Engine (IE) Region 11: 10 GbE 0 Region 12: 10 GbE 1 Region 15: PTT BUG=b:319773700 TEST=Run `flashrom -VV` on MTL and see all the regions are printed out Change-Id: I3b164ce4ae84bfd523fcd8be416c5d13183ed632 Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/81356 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M ich_descriptors.c M ichspi.c M util/ich_descriptors_tool/ich_descriptors_tool.c 3 files changed, 10 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/ich_descriptors.c b/ich_descriptors.c index 7bdca61..b11a78d 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -439,7 +439,7 @@ { static const char *const region_names[] = { "Descr.", "BIOS", "ME", "GbE", "Platf.", "DevExp", "BIOS2", "unknown", - "EC/BMC", "unknown", "IE", "10GbE", "unknown", "unknown", "unknown", "unknown" + "EC/BMC", "unknown", "IE", "10GbE0", "10GbE1", "unknown", "unknown", "PTT" }; if (i >= ARRAY_SIZE(region_names)) { msg_pdbg2("%s: region index too high.\n", __func__); @@ -518,24 +518,24 @@ } size_t num_regions; - msg_pdbg2(" FD BIOS ME GbE Pltf Reg5 Reg6 Reg7 EC Reg9"); + msg_pdbg2(" FD BIOS ME GbE Pltf DE BIOS2 Reg7 EC DE2 "); if (cs == CHIPSET_100_SERIES_SUNRISE_POINT) { num_regions = 10; msg_pdbg2("\n"); } else { num_regions = 16; - msg_pdbg2(" RegA RegB RegC RegD RegE RegF\n"); + msg_pdbg2(" IE 10GbE0 10GbE1 RegD RegE PTT \n"); } for (i = 0; i < nm; i++) { const unsigned int ext_region_start = 12; size_t j; msg_pdbg2("%-4s", master_names[i]); for (j = 0; j < (size_t)min(num_regions, ext_region_start); j++) - msg_pdbg2(" %c%c ", + msg_pdbg2(" %c%c ", desc->master.mstr[i].read & (1 << j) ? 'r' : ' ', desc->master.mstr[i].write & (1 << j) ? 'w' : ' '); for (j = ext_region_start; j < num_regions; j++) - msg_pdbg2(" %c%c ", + msg_pdbg2(" %c%c ", desc->master.mstr[i].ext_read & (1 << (j - ext_region_start)) ? 'r' : ' ', desc->master.mstr[i].ext_write & (1 << (j - ext_region_start)) ? 'w' : ' '); msg_pdbg2("\n"); diff --git a/ichspi.c b/ichspi.c index 36a7b3b..bee5ec9 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1840,7 +1840,8 @@ static const char *const region_names[] = { "Flash Descriptor", "BIOS", "Management Engine", "Gigabit Ethernet", "Platform Data", "Device Expansion", - "BIOS2", "unknown", "EC/BMC", + "BIOS2", "unknown", "EC/BMC", "Device Expansion 2", + "Innovation Engine", "10GbE0", "10GbE1", "unknown", "unknown", "PTT", }; const char *const region_name = i < ARRAY_SIZE(region_names) ? region_names[i] : "unknown"; diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index a5a59ad..844d8e9 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -38,9 +38,9 @@ static const char *const region_names[] = { "Descriptor", "BIOS", "ME", "GbE", "Platform", - "Region5", "BIOS2", "Region7", "EC/BMC", "Region9", - "IE", "10GbE", "Region12", "Region13", "Region14", - "Region15" + "DevExp", "BIOS2", "Region7", "EC/BMC", "DevExp2", + "IE", "10GbE0", "10GbE1", "Region13", "Region14", + "PTT" }; static void dump_file(const char *prefix, const uint32_t *dump, unsigned int len, -- To view, visit https://review.coreboot.org/c/flashrom/+/81356?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I3b164ce4ae84bfd523fcd8be416c5d13183ed632 Gerrit-Change-Number: 81356 Gerrit-PatchSet: 8 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-CC: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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[L] Change in flashrom[main]: doc: Convert serprog docs to rst and add to doc directory
by Anastasia Klimchuk (Code Review) 20 Apr '24

20 Apr '24

Attention is currently required from: Riku Viitanen, Swift Geek (Sebastian Grzywna), Sydney, Thomas Heijligen, Urja Rannikko. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/82018?usp=email ) Change subject: doc: Convert serprog docs to rst and add to doc directory ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I tried to gather people who know about serprog, or did development recently. One person I was not able to contact is GNUtoo, if someone knows how to contact them and invite to review, that would be great! Many thanks for review! I have converted existing docs to rst format, fixed few typos and removed broken links. Otherwise, it's the same content. -- To view, visit https://review.coreboot.org/c/flashrom/+/82018?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ie52f1e051ed215d61d5fb535e3eddeac71f64d13 Gerrit-Change-Number: 82018 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: Sydney <git(a)funkeleinhorn.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Urja Rannikko <urjaman(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Urja Rannikko <urjaman(a)gmail.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Sydney <git(a)funkeleinhorn.com> Gerrit-Attention: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Comment-Date: Sat, 20 Apr 2024 13:54:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in flashrom[main]: doc: Convert serprog docs to rst and add to doc directory
by Anastasia Klimchuk (Code Review) 20 Apr '24

20 Apr '24

Attention is currently required from: Riku Viitanen, Swift Geek (Sebastian Grzywna), Sydney, Thomas Heijligen, Urja Rannikko. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/82018?usp=email ) Change subject: doc: Convert serprog docs to rst and add to doc directory ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: For reference, wiki page is here https://wiki.flashrom.org/Serprog -- To view, visit https://review.coreboot.org/c/flashrom/+/82018?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ie52f1e051ed215d61d5fb535e3eddeac71f64d13 Gerrit-Change-Number: 82018 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: Sydney <git(a)funkeleinhorn.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Urja Rannikko <urjaman(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Urja Rannikko <urjaman(a)gmail.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Sydney <git(a)funkeleinhorn.com> Gerrit-Attention: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Comment-Date: Sat, 20 Apr 2024 13:50:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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