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Change subject: udelay: only use OS time for delays, except on DOS
......................................................................
Patch Set 9:
(1 comment)
File tests/udelay.c:
https://review.coreboot.org/c/flashrom/+/81545/comment/0fb34cc2_07d484b8 :
PS9, Line 41: This test could fail spuriously on a heavily-loaded system
> > do you think it would be reasonable to maintain this assertion as-is provided we ensure the tested […]
Brian, you have good points. Thank you for sharing your valuable experience!
I had this thought about guarding against infinite loop (if this is a useful thing?), but for this any large upper bound will do, can be 100x or anything
Peter maybe I will leave it to you to decide. I am so happy that you added a test!
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Change subject: flashchips: Split and add write-protect support for MX25L12833F
......................................................................
Patch Set 3:
(1 comment)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/81792/comment/fd137ffc_6bfb3245 :
PS2, Line 9008: MX25L12833F/MX25L12835F/MX25L12845E/MX25L12865E/MX25L12873F
> This is multi-chip entry, and two of them MX25L12845E and MX25L12865E has no configuration register. […]
Split into:
* "MX25L12833F/MX25L12835F/MX25L12873F"
* "MX25L12845E/MX25L12865E"
I've checked all the datasheet, but I don't have other chips to test.
I noticed that MX25L12873F doesn't support HPM (hardware protection mode), but IIUC flashrom have nothing to do with it, so I kept it in the same entry.
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Hello Anastasia Klimchuk, Hsuan Ting Chen, Stefan Reinauer, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/81356?usp=email
to look at the new patch set (#6).
Change subject: ich: Add names for region 5, 9, 10, 11, 12, 15
......................................................................
ich: Add names for region 5, 9, 10, 11, 12, 15
Add Region 9 for Intel Meteor Lake; update missing regions.
* Include Region 9 as officially required for Intel Meteor Lake platform.
* Incorporate missing region names from https://github.com/coreboot/coreboot/blob/main/util/ifdtool/ifdtool.c for completeness.
Region 5: Device Expansion (DE or DevExp)
Region 9: Device Expansion 2 (DE2 or DevExp2)
Region 10: Innovation Engine (IE)
Region 11: 10 GbE 0
Region 12: 10 GbE 1
Region 15: PTT
BUG=b:319773700
TEST=Run `flashrom -VV` on MTL and see all the regions are printed out
Change-Id: I3b164ce4ae84bfd523fcd8be416c5d13183ed632
Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org>
---
M ich_descriptors.c
M ichspi.c
M util/ich_descriptors_tool/ich_descriptors_tool.c
3 files changed, 9 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/56/81356/6
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Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/81836?usp=email )
Change subject: flashchips: Add support for MXIC MX25L1633E
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/81836/comment/be3b8c1b_1f6251fa :
PS3, Line 9280: MACRONIX_MX25L1635D
Just one thing here: if you can please mention new chip MX25L1633E in a comment to existing macro MACRONIX_MX25L1635D in flashchips.h. Thanks!
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Change subject: flashchips: Add support for MXIC MX25L1636E
......................................................................
Patch Set 1:
(3 comments)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/81835/comment/7d13896d_1ae1a928 :
PS1, Line 9283: OTP: 64B total
I know it was like this before, but datasheets for both chips say 4k-bit secured OTP, so seems like it was wrong before. It should be 512B
https://review.coreboot.org/c/flashrom/+/81835/comment/45bf5729_a1dad53d :
PS1, Line 9284: FEATURE_CFGR
None of datasheets have configuration register?
https://review.coreboot.org/c/flashrom/+/81835/comment/052a50bd_5912daea :
PS1, Line 9313: .tb = {CONFIG, 3, OTP}
Same as above, none of datasheets have configuration register
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Change subject: udelay: only use OS time for delays, except on DOS
......................................................................
Patch Set 9:
(1 comment)
File tests/udelay.c:
https://review.coreboot.org/c/flashrom/+/81545/comment/e25e8253_31a03ad3 :
PS9, Line 41: This test could fail spuriously on a heavily-loaded system
> do you think it would be reasonable to maintain this assertion as-is provided we ensure the tested delay is always short enough to avoid sleeping?
Ah, sorry, thanks for the sleep vs delay callout. The delay loop likely doesn't have the same magnitude of an issue, although it theoretically is still present. I'm fine with "try and see" here.
> Jenkins seems to be happy with the test, as we see.
Sure, once. But what's to say it doesn't fail 1/100 times? 1/1000? Do we guarantee what system load is run on the same Jenkins instance (I know nothing about Jenkins)? What if we have 10 such 1% flaky tests? Or 100? Eventually, nobody trusts the tests.
This is especially close to my heart at the moment, because I've recently been spending more than a week de-flaking another open source project's test suite, which were full of sleep-related magic and race conditions. The lesson that came out of that for me is that just about any race condition can and will be exposed. (And yes, this test has a race condition baked in.)
But like I said, I'm not extremely concerned here, unless we see it start flaking in practice.
> I like more tests, not less! :)
Flaky tests can be worse, at scale. But maybe flashrom is isolated enough (and run in its own tiny test environment) that "scale" doesn't matter much.
> ChromeOS fork could perhaps make a small one line diff [...]
Yeah, if it does indeed flake much, we'd likely disable or modify the test on the CrOS side.
Anyway, I'd consider my original comment resolved, but Anastasia has other comments in here so I'll leave that up to her when to resolve.
Thanks!
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Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/81855?usp=email )
Change subject: util/list_yet_unsupported_chips.h: Fix path
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Ooh this has been broken for a while, include dir was introduced a while ago... […]
It is printing out all the flashes that are not supported (as advertised) as far as I could see.
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Change subject: flashchips: Add write-protect support for MX25L12833F
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Daniel, I remember you are currently updating write-protect for MXIC chips, so I thought to add you here in case you have comments.
As reviewer, you can add comments to a patch, or if you have no comments you can vote on the patch
(there is more info here https://flashrom.org/how_to_support_flashrom.html#code-reviews)
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