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Change subject: ite_ecfw: Implement support for flashing ITE ECs found on TUXEDO laptops
......................................................................
Patch Set 29:
(1 comment)
File ite_ecfw.c:
https://review.coreboot.org/c/flashrom/+/55715/comment/ec3651a4_0504d635
PS29, Line 411: }
> Yes, correct. […]
I trust you that we need to do this. The thing is, we need to ensure
flashrom actually does it. ;) Normally, there is no order enforced of
the blocks to be written. But in case of `write_mode == 0` this function
must be called with the last block last (and it mustn't be skipped) and
before that it must be called with the first block (so we know the first
KiB). Currently this happens by coincidence because the whole flash is
erased, the way the core flashrom code is written, we expect that
the last block of the contents to be flashed are not empty, and we
expect that the changes in contents need an erase. We could leave
comments everywhere about this (still with the risk that it breaks
because of changes somewhere else). Or we could try to find a way
to make it work by definition. A hunch tells me that the write
granularity could help there.
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Change subject: ite_ecfw: Implement support for flashing ITE ECs found on TUXEDO laptops
......................................................................
Patch Set 29:
(1 comment)
File ite_ecfw.c:
https://review.coreboot.org/c/flashrom/+/55715/comment/67f6d3e1_b65487b4
PS29, Line 411: }
> When we think about flashrom as an application to simply replace flash content, these problems are o […]
Yes, correct. Flashing the ec directly on hardware level is possible but not a good idea at runtime, since flashing would interfere with the currently running firmware. Thus, the ec firmware implements flashing with help of the scratch region, as Michal described. We have to comply with the logic implemented there.
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Change subject: ite_ecfw: Implement support for flashing ITE ECs found on TUXEDO laptops
......................................................................
Patch Set 29:
(2 comments)
Patchset:
PS29:
> I mean it should be fully included in `-p internal` eventually. The `internal` […]
Understood. It may be a good idea to merge it with internal programmer indeed.
File ite_ecfw.c:
https://review.coreboot.org/c/flashrom/+/55715/comment/ffb5fb1a_704ee98d
PS29, Line 411: }
> AFAICS, if we'd allow a partial erase, flashrom could decide to only write […]
When we think about flashrom as an application to simply replace flash content, these problems are only theoretical. But if we look at it hardware-wise, it is a different story. The main problem with this first kbyte is that it contains the code responsible for writing to the flash. This is a special scratch memory which is doublemapped to 8051 External Memory and ROM space. When the flashing process begins, the flash access routines are copied to the scratch ROM space 4KB where EC can safely execute them without worrying about the flash content (EC wouldn't be able to fetch code when the SPI flash is in WIP/busy state). The command that is sent when writing the first kilobyte probably indicates to the EC that:
1. The flash access is finished after it takes the first kilobyte to be flashed.
2. EC can switch back from scratch ROM to the flash ROM with the execution.
That is why it must be done at the end of flashing process.
I hope I didn't make any mistake here, Michael can confirm
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Change subject: layout: Change signature for prepare_layout_for_extraction
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Thanks for reply! :)
>
> > I'm not sure if I mentioned this somewhere already, the topic seems familiar. I kind of see this extract feature as CLI code.
>
> Sorry if I missed that! I don't remember, but maybe because extract feature was upstreamed earlier when I just started and I wasn't fully aware of all everything that going on.
Don't worry, if we discussed this somewhere else already, I lost track
of it anyway.
> My reasoning for this patch chain was to align with larger movement to make cli a libflashrom user, which means libflashrom is used from everywhere and needs to be tested.
Yes, I got that :) we need to adapt libflashrom API for this. Making
existing functions public isn't always the best way, though.
>
> > So far, we have kept libflashrom free from file i/o and some target environments just don't support it
>
> Maybe I am missing something, but I don't see `prepare_layout_for_extraction` doing file i/o at the moment? It is populating file names, which is prep step for i/o, but the i/o itself is done next in read operation.
That's right. But for prepare_layout_for_extraction() to be useful in the
libflashrom API, we'd need another function there that probably does what
write_buf_to_include_args() currently does. And that's doing file i/o.
Also, the description in your next patch says "Fill in file name". So I'd
say it's part of a file i/o concept.
It's why I generally prefer to discuss the coarse direction of a topic
on the mailing list first. Here on Gerrit, people are often focused to
bring patches in step-by-step, but sometimes the bigger picture is only
visible at the end of a patch train. It can be frustrating for both authors
and reviewers to see that the effort on prior reviews doesn't pan out. Or
worse, they might want to merge something that they consider wrong just
because they put all the effort into it.
> Maybe `prepare_layout_for_extraction` can be renamed into something more specific?
I would much prefer to discuss first if the whole topic belongs into
libflashrom or the CLI.
> I agree with keeping libflashrom free from file i/o.
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 )
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 13:
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/61854/comment/3f5e8bb5_db48dc19
PS7, Line 17: Without this synchronisation being implemented, flashrom is running
: into below error:
:
: Erasing and writing flash chip... Timeout error between offset
: 0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED!
: Uh oh. Erase/write failed. Checking if anything has changed.
> > > > > Please let me know if anything we need to help for moving this CL?
> > > >
> > > > What was said in the first message of the comment thread.
> > >
> > > I have reattempted to update the commit msg with setup details and replication steps.
> > >
> > > Please suggest if you need better wordings.
> >
> > Ping!
>
> Ping!
Ping!
https://review.coreboot.org/c/flashrom/+/61854/comment/b72f2717_64fa01e5
PS7, Line 25: TEST=Concurrent flashrom access is not throwing timeout.
> > > > > Please let me know if anything we need to help for moving this CL?
> > > >
> > > > What was said in the first message of the comment thread.
> > >
> > > I'm able to verify this change on eve device. Updated the same in the commit msg.
> >
> > Ping!
>
> Ping!
Ping!
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Change subject: ichspi: Add Alder Lake support
......................................................................
Patch Set 13:
(1 comment)
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/62251/comment/49b621cb_131210a5
PS12, Line 1041: return CHIPSET_600_SERIES_ALDER_POINT;
> Done
For completeness here, Sam reported back:
```
$ ./util/ich_descriptors_tool/ich_descriptors_tool -d -c "chipset" -f /tmp/image-nivviks.bin
The flash image has a size of 33554432 [0x2000000] bytes.
Assuming chipset '600 series Alder Point'.
=== Content Section ===
FLVALSIG 0x0ff0a55a
FLMAP0 0x00040003
FLMAP1 0x46100208
FLMAP2 0x001401b0
--- Details ---
NR (Number of Regions): 16
FRBA (Flash Region Base Address): 0x040
NC (Number of Components): 1
FCBA (Flash Component Base Address): 0x030
ISL (ICH/PCH/SoC Strap Length): 70
FISBA/FPSBA (Flash ICH/PCH/SoC Strap Base Addr): 0x100
NM (Number of Masters): 2
FMBA (Flash Master Base Address): 0x080
MSL/PSL (MCH/PROC Strap Length): 1
FMSBA (Flash MCH/PROC Strap Base Address): 0xb00
=== Component Section ===
FLCOMP 0x093000f6
FLILL 0xad604221
FLILL1 0xc7c4b9b7
--- Details ---
Component 1 density: 32 MB
Component 2 is not used.
Read Clock Frequency: 100 MHz
Read ID and Status Clock Freq.: 50 MHz
Write and Erase Clock Freq.: 50 MHz
Fast Read is supported.
Fast Read Clock Frequency: 50 MHz
Dual Output Fast Read Support: disabled
Invalid instruction 0: 0x21
Invalid instruction 1: 0x42
Invalid instruction 2: 0x60
Invalid instruction 3: 0xad
Invalid instruction 4: 0xb7
Invalid instruction 5: 0xb9
Invalid instruction 6: 0xc4
Invalid instruction 7: 0xc7
=== Region Section ===
FLREG0 0x00000000
FLREG1 0x1fff0500
FLREG2 0x04ff0001
FLREG3 0x00007fff
FLREG4 0x00007fff
FLREG5 0x00007fff
FLREG6 0x00007fff
FLREG7 0x00007fff
FLREG8 0x00007fff
FLREG9 0x00007fff
FLREG10 0x00007fff
FLREG11 0x00007fff
FLREG12 0x00007fff
FLREG13 0x00007fff
FLREG14 0x00007fff
FLREG15 0x00007fff
--- Details ---
Region 0 (Descr. ) 0x00000000 - 0x00000fff
Region 1 (BIOS ) 0x00500000 - 0x01ffffff
Region 2 (ME ) 0x00001000 - 0x004fffff
Region 3 (GbE ) is unused.
Region 4 (Platf. ) is unused.
Region 5 (DevExp ) is unused.
Region 6 (BIOS2 ) is unused.
Region 7 (unknown) is unused.
Region 8 (EC/BMC ) is unused.
Region 9 (unknown) is unused.
Region 10 (IE ) is unused.
Region 11 (10GbE ) is unused.
Region 12 (unknown) is unused.
Region 13 (unknown) is unused.
Region 14 (unknown) is unused.
Region 15 (unknown) is unused.
=== Master Section ===
FLMSTR1 0xffffffff
FLMSTR2 0xffffffff
--- Details ---
FD BIOS ME GbE Pltf Reg5 Reg6 Reg7 EC Reg9 RegA RegB RegC RegD RegE RegF
BIOS rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
ME rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
=== Upper Map Section ===
FLUMAP1 0xc0ff02df
--- Details ---
VTL (length in DWORDS) = 2
VTBA (base address) = 0x000df0
VSCC Table: 1 entries
JID0 = 0x0000471f
VSCC0 = 0x20152015
Manufacturer ID 0x1f, Device ID 0x4700
BES=0x1, WG=1, WSR=0, WEWS=1, EO=0x20
=== Softstraps ===
--- North/MCH/PROC (1 entries) ---
STRP0 = 0xffffffff
ISL (70) is greater than the current maximum of 23 entries.
Only the first 23 entries will be printed.
--- South/ICH/PCH (23 entries) ---
STRP0 = 0x00000000
STRP1 = 0x00000001
STRP2 = 0x0100000d
STRP3 = 0x022c4000
STRP4 = 0x0001087f
STRP5 = 0x00000000
STRP6 = 0x00000018
STRP7 = 0x00070003
STRP8 = 0x48030008
STRP9 = 0x00000000
STRP10 = 0x0eff0001
STRP11 = 0x0481fbf0
STRP12 = 0x00000000
STRP13 = 0x000f000c
STRP14 = 0x22224222
STRP15 = 0x22424222
STRP16 = 0x00000000
STRP17 = 0x00000000
STRP18 = 0x00ff0000
STRP19 = 0xc8800060
STRP20 = 0x36008645
STRP21 = 0x00000000
STRP22 = 0x00580e20
The meaning of the descriptor straps are unknown yet.
=== Dumping region files ===
Dumping 4096 bytes of the Descriptor region from 0x00000000-0x00000fff to /tmp/image-nivviks.bin.Descriptor.bin... done.
Dumping 28311552 bytes of the BIOS region from 0x00500000-0x01ffffff to /tmp/image-nivviks.bin.BIOS.bin... done.
Dumping 5238784 bytes of the ME region from 0x00001000-0x004fffff to /tmp/image-nivviks.bin.ME.bin... done.
The GbE region is unused and thus not dumped.
The Platform region is unused and thus not dumped.
The Region5 region is unused and thus not dumped.
The BIOS2 region is unused and thus not dumped.
The Region7 region is unused and thus not dumped.
The EC/BMC region is unused and thus not dumped.
The Region9 region is unused and thus not dumped.
The IE region is unused and thus not dumped.
The 10GbE region is unused and thus not dumped.
The Region12 region is unused and thus not dumped.
The Region13 region is unused and thus not dumped.
The Region14 region is unused and thus not dumped.
The Region15 region is unused and thus not dumped.
```
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