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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58477
to look at the new patch set (#40).
Change subject: flash.h,flashchips.c: add writeprotect bit layout map to chips
......................................................................
flash.h,flashchips.c: add writeprotect bit layout map to chips
This patch adds a register bit map `struct reg_bit_info`, with fields
for storing the register, bit index, and writability of each bit that
affects the chip's write protection. This allows writeprotect code to be
independent of the register layout of any specific chip. The new fields
have been filled out for example chips.
The representation is centered around describing how bits can be
accessed and modified, rather than the layout of registers. This is
generally easier to work with in code that needs to access specific bits
and typically requires specifying the locations of fewer bits overall.
BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
Change-Id: Id08d77e6d4ca5109c0d698271146d026dbc21284
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M flash.h
M flashchips.c
M writeprotect.h
3 files changed, 77 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/58477/40
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Nico Huber has abandoned this change. ( https://review.coreboot.org/c/flashrom/+/57589 )
Change subject: Revert "Add support for Intel Emmitsburg PCH"
......................................................................
Abandoned
We fixed the immediate trouble, original 3-line patch got still 3 lines wrong, though.
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/57589 )
Change subject: Revert "Add support for Intel Emmitsburg PCH"
......................................................................
Patch Set 3: -Code-Review
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Attention is currently required from: Sam McNally, Nico Huber, Rizwan Qureshi, Edward O'Callaghan, Angel Pons.
Hello Sam McNally, build bot (Jenkins), Subrata Banik, Rizwan Qureshi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/62251
to look at the new patch set (#12).
Change subject: ichspi: Add Alder Lake support
......................................................................
ichspi: Add Alder Lake support
Does exactly what it says on the tin.
BUG=b:220799648
TEST=```localhost ~ # flashrom --flash-name
<snip>
Found Programmer flash chip "Opaque flash chip" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000.
vendor="Programmer" name="Opaque flash chip"
```
Tested on Brya.
Change-Id: Ie66cf519df13f3391c41f5016b16a81ef3dfd4bf
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M chipset_enable.c
M ich_descriptors.c
M ichspi.c
M programmer.h
M util/ich_descriptors_tool/ich_descriptors_tool.c
5 files changed, 34 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/51/62251/12
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