March 2022 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: flashchips.c: add writeprotect support for more chips
by Nikolai Artemiev (Code Review) March 1, 2022

March 1, 2022

Attention is currently required from: Edward O'Callaghan, Nikolai Artemiev, Anastasia Klimchuk. Hello build bot (Jenkins), Edward O'Callaghan, Anastasia Klimchuk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/62214 to look at the new patch set (#20). Change subject: flashchips.c: add writeprotect support for more chips ...................................................................... flashchips.c: add writeprotect support for more chips Flashrom Chip name | Chip(s) tested ---------------------------------+---------------------------- AT25SL128A | EN25QH128 | GD25LQ128C/GD25LQ128D/GD25LQ128E | GD25LQ128DSIG GD25LQ64(B) | GD25LQ64CWIG GD25Q127C/GD25Q128C | GD25Q127CSIG, GD25Q128ESIG GD25Q256D | GD25Q256DYIG GD25Q64(B) | GD25Q64CSIG W25Q128.JW.DTR | W25Q128.V..M | W25Q128.W | W25Q256JV_M | W25Q256.V | W25Q64.W | XM25QH128C | XM25QH256C | Operations tested with physical chips where possible, others just checked against datasheets. BUG=b:182223106 BRANCH=none TEST=acivating ranges, wp enable/disable, wp status Change-Id: I7f3d4c4148056098a845b5c64308b0333ebda395 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M flashchips.c 1 file changed, 138 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/14/62214/20 -- To view, visit https://review.coreboot.org/c/flashrom/+/62214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7f3d4c4148056098a845b5c64308b0333ebda395 Gerrit-Change-Number: 62214 Gerrit-PatchSet: 20 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: libflashrom,linux_mtd: add linux_mtd writeprotect support
by Nikolai Artemiev (Code Review) March 1, 2022

March 1, 2022

Attention is currently required from: Edward O'Callaghan, Nikolai Artemiev, Anastasia Klimchuk. Hello build bot (Jenkins), Edward O'Callaghan, Anastasia Klimchuk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/61897 to look at the new patch set (#27). Change subject: libflashrom,linux_mtd: add linux_mtd writeprotect support ...................................................................... libflashrom,linux_mtd: add linux_mtd writeprotect support BUG=b:182223106 BRANCH=none TEST=make Change-Id: I5c86e28cdec44bec49ba1d36f8ab62241b9b01da Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M libflashrom.c M linux_mtd.c M programmer.h 3 files changed, 126 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/97/61897/27 -- To view, visit https://review.coreboot.org/c/flashrom/+/61897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5c86e28cdec44bec49ba1d36f8ab62241b9b01da Gerrit-Change-Number: 61897 Gerrit-PatchSet: 27 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: writeprotect: add get_wp_range() for decoding ranges
by Anastasia Klimchuk (Code Review) March 1, 2022

March 1, 2022

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/59183 ) Change subject: writeprotect: add get_wp_range() for decoding ranges ...................................................................... writeprotect: add get_wp_range() for decoding ranges BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom --wp-{status,range} at end of patch series Change-Id: I5a1dfcf384166b1bac319d286306747e1dcaa000 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59183 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M writeprotect.c 1 file changed, 11 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved diff --git a/writeprotect.c b/writeprotect.c index 20b5afc..ca9d9ec 100644 --- a/writeprotect.c +++ b/writeprotect.c @@ -150,9 +150,17 @@ return FLASHROM_WP_OK; } +/** Get the range selected by a WP configuration. */ +static enum flashrom_wp_result get_wp_range(struct wp_range *range, struct flashctx *flash, const struct wp_bits *bits) +{ + flash->chip->decode_range(&range->start, &range->len, bits, flashrom_flash_getsize(flash)); + + return FLASHROM_WP_OK; +} + static bool chip_supported(struct flashctx *flash) { - return false; + return (flash->chip != NULL) && (flash->chip->decode_range != NULL); } enum flashrom_wp_result wp_read_cfg(struct flashrom_wp_cfg *cfg, struct flashctx *flash) @@ -166,11 +174,11 @@ if (ret == FLASHROM_WP_OK) ret = read_wp_bits(&bits, flash); - /* TODO: implement get_wp_range() and get_wp_mode() and call them */ - /* if (ret == FLASHROM_WP_OK) ret = get_wp_range(&cfg->range, flash, &bits); + /* TODO: implement and get_wp_mode() and call it */ + /* if (ret == FLASHROM_WP_OK) ret = get_wp_mode(&cfg->mode, &bits); */ 42 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/flashrom/+/59183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5a1dfcf384166b1bac319d286306747e1dcaa000 Gerrit-Change-Number: 59183 Gerrit-PatchSet: 46 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: flashchips,writeprotect_ranges: add range decoding function
by Anastasia Klimchuk (Code Review) March 1, 2022

March 1, 2022

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/58480 ) Change subject: flashchips,writeprotect_ranges: add range decoding function ...................................................................... flashchips,writeprotect_ranges: add range decoding function Allow chips to specify functions that map status register bits to protection ranges. These are used to enumerate available ranges and determine the protection state of chips. The patch also adds a range decoding function for the example chips. Many other chips can also be handled by it, though some will require different functions (e.g. MX25L6406 and related chips). Another approach that has been tried in cros flashrom is maintaining tables of range data, but it quickly becomes error prone and hard to validate. Using a function to interpret the ranges allows compact encoding with most chips and is flexible enough to allow chips with less predictable ranges to be handled as well. BUG=b:195381327,b:153800563 BRANCH=none TEST=dumped range tables, checked against datasheets Change-Id: Id163ed80938a946a502ed116e48e8236e36eb203 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58480 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M Makefile M chipdrivers.h M flash.h M flashchips.c M meson.build A writeprotect_ranges.c 6 files changed, 107 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved Anastasia Klimchuk: Looks good to me, approved diff --git a/Makefile b/Makefile index 6841552..9a9628f 100644 --- a/Makefile +++ b/Makefile @@ -381,7 +381,8 @@ CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \ sst28sf040.o 82802ab.o \ sst49lfxxxc.o sst_fwhub.o edi.o flashchips.o spi.o spi25.o spi25_statusreg.o \ - spi95.o opaque.o sfdp.o en29lv640b.o at45db.o writeprotect.o s25f.o + spi95.o opaque.o sfdp.o en29lv640b.o at45db.o s25f.o \ + writeprotect.o writeprotect_ranges.o ############################################################################### # Library code. diff --git a/chipdrivers.h b/chipdrivers.h index ea8d480..c223534 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -216,4 +216,7 @@ int probe_spi_st95(struct flashctx *flash); int spi_block_erase_emulation(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +/* writeprotect_ranges.c */ +void decode_range_spi25(size_t *start, size_t *len, const struct wp_bits *, size_t chip_len); + #endif /* !__CHIPDRIVERS_H__ */ diff --git a/flash.h b/flash.h index b935e9b..f63aa5d 100644 --- a/flash.h +++ b/flash.h @@ -195,6 +195,8 @@ } writability; }; +struct wp_bits; + struct flashchip { const char *vendor; const char *name; @@ -305,6 +307,10 @@ /* Complement bit (CMP) */ struct reg_bit_info cmp; } reg_bits; + + /* Function that takes a set of WP config bits (e.g. BP, SEC, TB, etc) */ + /* and determines what protection range they select. */ + void (*decode_range)(size_t *start, size_t *len, const struct wp_bits *, size_t chip_len); }; typedef int (*chip_restore_fn_cb_t)(struct flashctx *flash, uint8_t status); diff --git a/flashchips.c b/flashchips.c index e12c8fc..acb7718 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6354,6 +6354,7 @@ .sec = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */ .cmp = {STATUS2, 6, RW}, }, + .decode_range = decode_range_spi25, }, { @@ -6760,6 +6761,7 @@ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, .tb = {STATUS1, 6, RW}, }, + .decode_range = decode_range_spi25, }, { @@ -6808,6 +6810,7 @@ .sec = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */ .cmp = {STATUS2, 6, RW}, }, + .decode_range = decode_range_spi25, }, { diff --git a/meson.build b/meson.build index 367c48a..cc393a7 100644 --- a/meson.build +++ b/meson.build @@ -429,6 +429,7 @@ srcs += 'w29ee011.c' srcs += 'w39.c' srcs += 'writeprotect.c' +srcs += 'writeprotect_ranges.c' mapfile = 'libflashrom.map' vflag = '-Wl,--version-script,@0@/@1@'.format(meson.current_source_dir(), mapfile) diff --git a/writeprotect_ranges.c b/writeprotect_ranges.c new file mode 100644 index 0000000..dacce32 --- /dev/null +++ b/writeprotect_ranges.c @@ -0,0 +1,92 @@ +/* + * This file is part of the flashrom project. + * + * Copyright 2021 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "writeprotect.h" +#include "chipdrivers.h" + +/* + * Protection range calculation that works with many common SPI flash chips. + */ +void decode_range_spi25(size_t *start, size_t *len, const struct wp_bits *bits, size_t chip_len) +{ + /* Interpret BP bits as an integer */ + size_t bp = 0; + size_t bp_max = 0; + + for (size_t i = 0; i < bits->bp_bit_count; i++) { + bp |= bits->bp[i] << i; + bp_max |= 1 << i; + } + + if (bp == 0) { + /* Special case: all BP bits are 0 => no write protection */ + *len = 0; + } else if (bp == bp_max) { + /* Special case: all BP bits are 1 => full write protection */ + *len = chip_len; + } else { + /* + * Usual case: the BP bits encode a coefficient in the form + * `coeff = 2 ** (bp - 1)`. + * + * The range's length is given by multiplying the coefficient + * by a base unit, usually a 4K sector or a 64K block. + */ + + size_t coeff = 1 << (bp - 1); + size_t max_coeff = 1 << (bp_max - 2); + + size_t sector_len = 4 * KiB; + size_t default_block_len = 64 * KiB; + + if (bits->sec_bit_present && bits->sec == 1) { + /* + * SEC=1, protect 4K sectors. Flash chips clamp the + * protection length at 32K, probably to avoid overlap + * with the SEC=0 case. + */ + *len = min(sector_len * coeff, default_block_len / 2); + } else { + /* + * SEC=0 or is not present, protect blocks. + * + * With very large chips, the 'block' size can be + * larger than 64K. This occurs when a larger block + * size is needed so that half the chip can be + * protected by the maximum possible coefficient. + */ + size_t min_block_len = chip_len / 2 / max_coeff; + size_t block_len = max(min_block_len, default_block_len); + + *len = min(block_len * coeff, chip_len); + } + } + + /* Apply TB bit */ + bool protect_top = bits->tb_bit_present ? (bits->tb == 0) : 1; + + /* Apply CMP bit */ + if (bits->cmp_bit_present && bits->cmp == 1) { + *len = chip_len - *len; + protect_top = !protect_top; + } + + /* Calculate start address, ensuring that empty ranges start at 0 */ + if (protect_top && *len > 0) + *start = chip_len - *len; + else + *start = 0; +} 44 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/flashrom/+/58480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id163ed80938a946a502ed116e48e8236e36eb203 Gerrit-Change-Number: 58480 Gerrit-PatchSet: 51 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: libflashrom,writeprotect: add functions for reading/writing WP configs
by Anastasia Klimchuk (Code Review) March 1, 2022

March 1, 2022

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/58479 ) Change subject: libflashrom,writeprotect: add functions for reading/writing WP configs ...................................................................... libflashrom,writeprotect: add functions for reading/writing WP configs New functions are exposed through the libflashrom API for reading/writing chip's WP settins: `flashrom_wp_{read,write}_cfg()`. They read/write an opaque `struct flashrom_wp_cfg` instance, which includes the flash protection range and status register protection mode. This commit also adds `{read,write}_wp_bits()` helper functions that read/write chip-specific WP configuration bits. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series Change-Id: I3ad25708c3321b8fb0216c3eaf6ffc07616537ad Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58479 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M libflashrom.c M libflashrom.h M writeprotect.c M writeprotect.h 4 files changed, 363 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved Anastasia Klimchuk: Looks good to me, approved diff --git a/libflashrom.c b/libflashrom.c index 5f14c68..f0b9cfd 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -31,6 +31,7 @@ #include "layout.h" #include "ich_descriptors.h" #include "libflashrom.h" +#include "writeprotect.h" /** * @defgroup flashrom-general General @@ -623,3 +624,127 @@ } /** @} */ /* end flashrom-layout */ + + +/** + * @defgroup flashrom-wp + * @{ + */ + +/** + * @brief Create a new empty WP configuration. + * + * @param[out] cfg Points to a pointer of type struct flashrom_wp_cfg that will + * be set if creation succeeds. *cfg has to be freed by the + * caller with @ref flashrom_wp_cfg_release. + * @return 0 on success + * >0 on failure + */ +enum flashrom_wp_result flashrom_wp_cfg_new(struct flashrom_wp_cfg **cfg) +{ + *cfg = calloc(1, sizeof(**cfg)); + return *cfg ? 0 : FLASHROM_WP_ERR_OTHER; +} + +/** + * @brief Free a WP configuration. + * + * @param[out] cfg Pointer to the flashrom_wp_cfg to free. + */ +void flashrom_wp_cfg_release(struct flashrom_wp_cfg *cfg) +{ + free(cfg); +} + +/** + * @brief Set the protection mode for a WP configuration. + * + * @param[in] mode The protection mode to set. + * @param[out] cfg Pointer to the flashrom_wp_cfg structure to modify. + */ +void flashrom_wp_set_mode(struct flashrom_wp_cfg *cfg, enum flashrom_wp_mode mode) +{ + cfg->mode = mode; +} + +/** + * @brief Get the protection mode from a WP configuration. + * + * @param[in] cfg The WP configuration to get the protection mode from. + * @return The configuration's protection mode. + */ +enum flashrom_wp_mode flashrom_wp_get_mode(const struct flashrom_wp_cfg *cfg) +{ + return cfg->mode; +} + +/** + * @brief Set the protection range for a WP configuration. + * + * @param[out] cfg Pointer to the flashrom_wp_cfg structure to modify. + * @param[in] start The range's start address. + * @param[in] len The range's length. + */ +void flashrom_wp_set_range(struct flashrom_wp_cfg *cfg, size_t start, size_t len) +{ + cfg->range.start = start; + cfg->range.len = len; +} + +/** + * @brief Get the protection range from a WP configuration. + * + * @param[out] start Points to a size_t to write the range start to. + * @param[out] len Points to a size_t to write the range length to. + * @param[in] cfg The WP configuration to get the range from. + */ +void flashrom_wp_get_range(size_t *start, size_t *len, const struct flashrom_wp_cfg *cfg) +{ + *start = cfg->range.start; + *len = cfg->range.len; +} + +/** + * @brief Write a WP configuration to a flash chip. + * + * @param[in] flash The flash context used to access the chip. + * @param[in] cfg The WP configuration to write to the chip. + * @return 0 on success + * >0 on failure + */ +enum flashrom_wp_result flashrom_wp_write_cfg(struct flashctx *flash, const struct flashrom_wp_cfg *cfg) +{ + /* + * TODO: Call custom implementation if the programmer is opaque, as + * direct WP operations require SPI access. In particular, linux_mtd + * has its own WP operations we should use instead. + */ + if (flash->mst->buses_supported & BUS_SPI) + return wp_write_cfg(flash, cfg); + + return FLASHROM_WP_ERR_OTHER; +} + +/** + * @brief Read the current WP configuration from a flash chip. + * + * @param[out] cfg Pointer to a struct flashrom_wp_cfg to store the chip's + * configuration in. + * @param[in] flash The flash context used to access the chip. + * @return 0 on success + * >0 on failure + */ +enum flashrom_wp_result flashrom_wp_read_cfg(struct flashrom_wp_cfg *cfg, struct flashctx *flash) +{ + /* + * TODO: Call custom implementation if the programmer is opaque, as + * direct WP operations require SPI access. In particular, linux_mtd + * has its own WP operations we should use instead. + */ + if (flash->mst->buses_supported & BUS_SPI) + return wp_read_cfg(cfg, flash); + + return FLASHROM_WP_ERR_OTHER; +} + +/** @} */ /* end flashrom-wp */ diff --git a/libflashrom.h b/libflashrom.h index 1c9498e..6d02d50 100644 --- a/libflashrom.h +++ b/libflashrom.h @@ -1,6 +1,7 @@ /* * This file is part of the flashrom project. * + * Copyright (C) 2010 Google Inc. * Copyright (C) 2012 secunet Security Networks AG * (Written by Nico Huber <nico.huber(a)secunet.com> for secunet) * @@ -119,4 +120,32 @@ void flashrom_layout_release(struct flashrom_layout *); void flashrom_layout_set(struct flashrom_flashctx *, const struct flashrom_layout *); +/** @ingroup flashrom-wp */ +enum flashrom_wp_result { + FLASHROM_WP_OK = 0, + FLASHROM_WP_ERR_CHIP_UNSUPPORTED = 1, + FLASHROM_WP_ERR_OTHER = 2, + FLASHROM_WP_ERR_READ_FAILED = 3, + FLASHROM_WP_ERR_WRITE_FAILED = 4, + FLASHROM_WP_ERR_VERIFY_FAILED = 5 +}; + +enum flashrom_wp_mode { + FLASHROM_WP_MODE_DISABLED, + FLASHROM_WP_MODE_HARDWARE, + FLASHROM_WP_MODE_POWER_CYCLE, + FLASHROM_WP_MODE_PERMANENT +}; +struct flashrom_wp_cfg; + +enum flashrom_wp_result flashrom_wp_cfg_new(struct flashrom_wp_cfg **); +void flashrom_wp_cfg_release(struct flashrom_wp_cfg *); +void flashrom_wp_set_mode(struct flashrom_wp_cfg *, enum flashrom_wp_mode); +enum flashrom_wp_mode flashrom_wp_get_mode(const struct flashrom_wp_cfg *); +void flashrom_wp_set_range(struct flashrom_wp_cfg *, size_t start, size_t len); +void flashrom_wp_get_range(size_t *start, size_t *len, const struct flashrom_wp_cfg *); + +enum flashrom_wp_result flashrom_wp_read_cfg(struct flashrom_wp_cfg *, struct flashrom_flashctx *); +enum flashrom_wp_result flashrom_wp_write_cfg(struct flashrom_flashctx *, const struct flashrom_wp_cfg *); + #endif /* !__LIBFLASHROM_H__ */ diff --git a/writeprotect.c b/writeprotect.c index cfcb13c..20b5afc 100644 --- a/writeprotect.c +++ b/writeprotect.c @@ -23,3 +23,191 @@ #include "libflashrom.h" #include "chipdrivers.h" #include "writeprotect.h" + +/** Read and extract a single bit from the chip's registers */ +static enum flashrom_wp_result read_bit(uint8_t *value, bool *present, struct flashctx *flash, struct reg_bit_info bit) +{ + *present = bit.reg != INVALID_REG; + if (*present) { + if (spi_read_register(flash, bit.reg, value)) + return FLASHROM_WP_ERR_READ_FAILED; + *value = (*value >> bit.bit_index) & 1; + } else { + /* Zero bit, it may be used by compare_ranges(). */ + *value = 0; + } + + return FLASHROM_WP_OK; +} + +/** Read all WP configuration bits from the chip's registers. */ +static enum flashrom_wp_result read_wp_bits(struct wp_bits *bits, struct flashctx *flash) +{ + /* + * For each WP bit that is included in the chip's register layout, read + * the register that contains it, extracts the bit's value, and assign + * it to the appropriate field in the wp_bits structure. + */ + const struct reg_bit_map *bit_map = &flash->chip->reg_bits; + bool ignored; + size_t i; + enum flashrom_wp_result ret; + + ret = read_bit(&bits->tb, &bits->tb_bit_present, flash, bit_map->tb); + if (ret != FLASHROM_WP_OK) + return ret; + + ret = read_bit(&bits->sec, &bits->sec_bit_present, flash, bit_map->sec); + if (ret != FLASHROM_WP_OK) + return ret; + + ret = read_bit(&bits->cmp, &bits->cmp_bit_present, flash, bit_map->cmp); + if (ret != FLASHROM_WP_OK) + return ret; + + ret = read_bit(&bits->srp, &bits->srp_bit_present, flash, bit_map->srp); + if (ret != FLASHROM_WP_OK) + return ret; + + ret = read_bit(&bits->srl, &bits->srl_bit_present, flash, bit_map->srl); + if (ret != FLASHROM_WP_OK) + return ret; + + for (i = 0; i < ARRAY_SIZE(bits->bp); i++) { + if (bit_map->bp[i].reg == INVALID_REG) + break; + + bits->bp_bit_count = i + 1; + ret = read_bit(&bits->bp[i], &ignored, flash, bit_map->bp[i]); + if (ret != FLASHROM_WP_OK) + return ret; + } + + return ret; +} + +/** Helper function for write_wp_bits(). */ +static void set_reg_bit( + uint8_t *reg_values, uint8_t *write_masks, + struct reg_bit_info bit, uint8_t value) +{ + if (bit.reg != INVALID_REG) { + reg_values[bit.reg] |= value << bit.bit_index; + write_masks[bit.reg] |= 1 << bit.bit_index; + } +} + +/** Write WP configuration bits to the flash's registers. */ +static enum flashrom_wp_result write_wp_bits(struct flashctx *flash, struct wp_bits bits) +{ + size_t i; + const struct reg_bit_map *reg_bits = &flash->chip->reg_bits; + + /* Convert wp_bits to register values and write masks */ + uint8_t reg_values[MAX_REGISTERS] = {0}; + uint8_t write_masks[MAX_REGISTERS] = {0}; + + for (i = 0; i < bits.bp_bit_count; i++) + set_reg_bit(reg_values, write_masks, reg_bits->bp[i], bits.bp[i]); + + set_reg_bit(reg_values, write_masks, reg_bits->tb, bits.tb); + set_reg_bit(reg_values, write_masks, reg_bits->sec, bits.sec); + set_reg_bit(reg_values, write_masks, reg_bits->cmp, bits.cmp); + set_reg_bit(reg_values, write_masks, reg_bits->srp, bits.srp); + set_reg_bit(reg_values, write_masks, reg_bits->srl, bits.srl); + + /* Write each register */ + for (enum flash_reg reg = STATUS1; reg < MAX_REGISTERS; reg++) { + if (!write_masks[reg]) + continue; + + uint8_t value; + if (spi_read_register(flash, reg, &value)) + return FLASHROM_WP_ERR_READ_FAILED; + + value = (value & ~write_masks[reg]) | (reg_values[reg] & write_masks[reg]); + + if (spi_write_register(flash, reg, value)) + return FLASHROM_WP_ERR_WRITE_FAILED; + } + + /* Verify each register */ + for (enum flash_reg reg = STATUS1; reg < MAX_REGISTERS; reg++) { + if (!write_masks[reg]) + continue; + + uint8_t value; + if (spi_read_register(flash, reg, &value)) + return FLASHROM_WP_ERR_READ_FAILED; + + uint8_t actual = value & write_masks[reg]; + uint8_t expected = reg_values[reg] & write_masks[reg]; + + if (actual != expected) + return FLASHROM_WP_ERR_VERIFY_FAILED; + } + + return FLASHROM_WP_OK; +} + +static bool chip_supported(struct flashctx *flash) +{ + return false; +} + +enum flashrom_wp_result wp_read_cfg(struct flashrom_wp_cfg *cfg, struct flashctx *flash) +{ + struct wp_bits bits; + enum flashrom_wp_result ret = FLASHROM_WP_OK; + + if (!chip_supported(flash)) + ret = FLASHROM_WP_ERR_CHIP_UNSUPPORTED; + + if (ret == FLASHROM_WP_OK) + ret = read_wp_bits(&bits, flash); + + /* TODO: implement get_wp_range() and get_wp_mode() and call them */ + /* + if (ret == FLASHROM_WP_OK) + ret = get_wp_range(&cfg->range, flash, &bits); + + if (ret == FLASHROM_WP_OK) + ret = get_wp_mode(&cfg->mode, &bits); + */ + + return ret; +} + +enum flashrom_wp_result wp_write_cfg(struct flashctx *flash, const struct flashrom_wp_cfg *cfg) +{ + struct wp_bits bits; + enum flashrom_wp_result ret = FLASHROM_WP_OK; + + if (!chip_supported(flash)) + ret = FLASHROM_WP_ERR_CHIP_UNSUPPORTED; + + if (ret == FLASHROM_WP_OK) + ret = read_wp_bits(&bits, flash); + + /* Set protection range */ + /* TODO: implement set_wp_range() and use it */ + /* + if (ret == FLASHROM_WP_OK) + ret = set_wp_range(&bits, flash, cfg->range); + if (ret == FLASHROM_WP_OK) + ret = write_wp_bits(flash, bits); + */ + + /* Set protection mode */ + /* TODO: implement set_wp_mode() and use it */ + /* + if (ret == FLASHROM_WP_OK) + ret = set_wp_mode(&bits, cfg->mode); + */ + if (ret == FLASHROM_WP_OK) + ret = write_wp_bits(flash, bits); + + return ret; +} + +/** @} */ /* end flashrom-wp */ diff --git a/writeprotect.h b/writeprotect.h index 2f473f7..d54befa 100644 --- a/writeprotect.h +++ b/writeprotect.h @@ -22,8 +22,21 @@ #include <stdbool.h> #include <stddef.h> +#include "libflashrom.h" + #define MAX_BP_BITS 4 +/* Chip protection range: start address and length. */ +struct wp_range { + size_t start, len; +}; + +/* Generic description of a chip's write protection configuration. */ +struct flashrom_wp_cfg { + enum flashrom_wp_mode mode; + struct wp_range range; +}; + /* * Description of a chip's write protection configuration. * @@ -56,4 +69,12 @@ uint8_t bp[MAX_BP_BITS]; }; +struct flashrom_flashctx; + +/* Write WP configuration to the chip */ +enum flashrom_wp_result wp_write_cfg(struct flashrom_flashctx *, const struct flashrom_wp_cfg *); + +/* Read WP configuration from the chip */ +enum flashrom_wp_result wp_read_cfg(struct flashrom_wp_cfg *, struct flashrom_flashctx *); + #endif /* !__WRITEPROTECT_H__ */ 43 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/flashrom/+/58479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3ad25708c3321b8fb0216c3eaf6ffc07616537ad Gerrit-Change-Number: 58479 Gerrit-PatchSet: 48 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: merged

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Change in flashrom[master]: writeprotect.h: add structure to represent chip wp configuration bits
by Anastasia Klimchuk (Code Review) March 1, 2022

March 1, 2022

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/58478 ) Change subject: writeprotect.h: add structure to represent chip wp configuration bits ...................................................................... writeprotect.h: add structure to represent chip wp configuration bits Add `struct wp_bits` for representing values of all WP bits in a chip's status/config register(s). It allows most WP code to store and manipulate a chip's configuration without knowing the exact layout of bits in the chip's status registers. Supporting other chips may require additional fields to be added to the structure. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series Change-Id: I17dee630248ce7b51e624a6e46d7097d5d0de809 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58478 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M writeprotect.h 1 file changed, 36 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved Anastasia Klimchuk: Looks good to me, approved diff --git a/writeprotect.h b/writeprotect.h index 8510226..2f473f7 100644 --- a/writeprotect.h +++ b/writeprotect.h @@ -18,6 +18,42 @@ #ifndef __WRITEPROTECT_H__ #define __WRITEPROTECT_H__ 1 +#include <stdint.h> +#include <stdbool.h> +#include <stddef.h> + #define MAX_BP_BITS 4 +/* + * Description of a chip's write protection configuration. + * + * It allows most WP code to store and manipulate a chip's configuration + * without knowing the exact layout of bits in the chip's status registers. + */ +struct wp_bits { + /* Status register protection bit (SRP) */ + bool srp_bit_present; + uint8_t srp; + + /* Status register lock bit (SRL) */ + bool srl_bit_present; + uint8_t srl; + + /* Complement bit (CMP) */ + bool cmp_bit_present; + uint8_t cmp; + + /* Sector/block protection bit (SEC) */ + bool sec_bit_present; + uint8_t sec; + + /* Top/bottom protection bit (TB) */ + bool tb_bit_present; + uint8_t tb; + + /* Block protection bits (BP) */ + size_t bp_bit_count; + uint8_t bp[MAX_BP_BITS]; +}; + #endif /* !__WRITEPROTECT_H__ */ 38 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/flashrom/+/58478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I17dee630248ce7b51e624a6e46d7097d5d0de809 Gerrit-Change-Number: 58478 Gerrit-PatchSet: 43 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: writeprotect.h: add structure to represent chip wp configuration bits
by Nikolai Artemiev (Code Review) March 1, 2022

March 1, 2022

Attention is currently required from: Angel Pons, Nikolai Artemiev, Sergii Dmytruk. Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/58478 to look at the new patch set (#42). Change subject: writeprotect.h: add structure to represent chip wp configuration bits ...................................................................... writeprotect.h: add structure to represent chip wp configuration bits Add `struct wp_bits` for representing values of all WP bits in a chip's status/config register(s). It allows most WP code to store and manipulate a chip's configuration without knowing the exact layout of bits in the chip's status registers. Supporting other chips may require additional fields to be added to the structure. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series Change-Id: I17dee630248ce7b51e624a6e46d7097d5d0de809 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M writeprotect.h 1 file changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/58478/42 -- To view, visit https://review.coreboot.org/c/flashrom/+/58478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I17dee630248ce7b51e624a6e46d7097d5d0de809 Gerrit-Change-Number: 58478 Gerrit-PatchSet: 42 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: libflashrom,writeprotect: add flashrom_wp_get_available_ranges()
by Nikolai Artemiev (Code Review) March 1, 2022

March 1, 2022

Attention is currently required from: Angel Pons, Nikolai Artemiev, Sergii Dmytruk. Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/58481 to look at the new patch set (#61). Change subject: libflashrom,writeprotect: add flashrom_wp_get_available_ranges() ...................................................................... libflashrom,writeprotect: add flashrom_wp_get_available_ranges() Generate list of available ranges by enumerating all possible values that range bits (BPx, TB, ...) can take and using the chip's range decoding function to get the range that is selected by each one. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom --wp-list Change-Id: Id51f038f03305c8536d80313e52f77d27835f34d Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M libflashrom.c M libflashrom.h M writeprotect.c M writeprotect.h 4 files changed, 281 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/81/58481/61 -- To view, visit https://review.coreboot.org/c/flashrom/+/58481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id51f038f03305c8536d80313e52f77d27835f34d Gerrit-Change-Number: 58481 Gerrit-PatchSet: 61 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: writeprotect: add set_wp_range()
by Nikolai Artemiev (Code Review) March 1, 2022

March 1, 2022

Attention is currently required from: Angel Pons, Nikolai Artemiev, Anastasia Klimchuk, Sergii Dmytruk. Hello build bot (Jenkins), Nico Huber, Paul Menzel, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/58482 to look at the new patch set (#64). Change subject: writeprotect: add set_wp_range() ...................................................................... writeprotect: add set_wp_range() BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom --wp-{status,range} Change-Id: I7d26f43fb05c5828b9839bb57a28fa1088dcd9a0 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M libflashrom.h M writeprotect.c 2 files changed, 36 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/82/58482/64 -- To view, visit https://review.coreboot.org/c/flashrom/+/58482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7d26f43fb05c5828b9839bb57a28fa1088dcd9a0 Gerrit-Change-Number: 58482 Gerrit-PatchSet: 64 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: spi25_statusreg: inline spi_write_register_flag()
by Nikolai Artemiev (Code Review) March 1, 2022

March 1, 2022

Attention is currently required from: Nico Huber, Edward O'Callaghan, Nikolai Artemiev, Sergii Dmytruk. Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/59528 to look at the new patch set (#58). Change subject: spi25_statusreg: inline spi_write_register_flag() ...................................................................... spi25_statusreg: inline spi_write_register_flag() Creating the entire SPI command that should be sent to the chip in spi_write_register() is simpler than splitting it across two functions that have to pass multiple parameters between them. Additionally, having separate spi_write_register_flag() function provided little benefit, as it was only ever called from spi_write_register(). BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom -{r,w,E} Change-Id: I4996b0848d0ed09032bad2ab13ab1f40bbfc0304 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M spi25_statusreg.c 1 file changed, 56 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/28/59528/58 -- To view, visit https://review.coreboot.org/c/flashrom/+/59528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I4996b0848d0ed09032bad2ab13ab1f40bbfc0304 Gerrit-Change-Number: 59528 Gerrit-PatchSet: 58 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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