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to look at the new patch set (#50).
Change subject: flashchips,writeprotect_ranges: add range decoding function
......................................................................
flashchips,writeprotect_ranges: add range decoding function
Allow chips to specify functions that map status register bits to
protection ranges. These are used to enumerate available ranges and
determine the protection state of chips. The patch also adds a range
decoding function for the example chips. Many other chips can also be
handled by it, though some will require different functions (e.g.
MX25L6406 and related chips).
Another approach that has been tried in cros flashrom is maintaining
tables of range data, but it quickly becomes error prone and hard to
validate.
Using a function to interpret the ranges allows compact encoding with
most chips and is flexible enough to allow chips with less predictable
ranges to be handled as well.
BUG=b:195381327,b:153800563
BRANCH=none
TEST=dumped range tables, checked against datasheets
Change-Id: Id163ed80938a946a502ed116e48e8236e36eb203
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M Makefile
M chipdrivers.h
M flash.h
M flashchips.c
M meson.build
A writeprotect_ranges.c
6 files changed, 107 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/80/58480/50
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58479
to look at the new patch set (#47).
Change subject: libflashrom,writeprotect: add functions for reading/writing WP configs
......................................................................
libflashrom,writeprotect: add functions for reading/writing WP configs
New functions are exposed through the libflashrom API for
reading/writing chip's WP settins: `flashrom_wp_{read,write}_cfg()`.
They read/write an opaque `struct flashrom_wp_cfg` instance, which
includes the flash protection range and status register protection mode.
This commit also adds `{read,write}_wp_bits()` helper functions that
read/write chip-specific WP configuration bits.
BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
Change-Id: I3ad25708c3321b8fb0216c3eaf6ffc07616537ad
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M libflashrom.c
M libflashrom.h
M writeprotect.c
M writeprotect.h
4 files changed, 363 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/58479/47
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/59528
to look at the new patch set (#58).
Change subject: spi25_statusreg: inline spi_write_register_flag()
......................................................................
spi25_statusreg: inline spi_write_register_flag()
Creating the entire SPI command that should be sent to the chip in
spi_write_register() is simpler than splitting it across two functions
that have to pass multiple parameters between them.
Additionally, having separate spi_write_register_flag() function
provided little benefit, as it was only ever called from
spi_write_register().
BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom -{r,w,E}
Change-Id: I4996b0848d0ed09032bad2ab13ab1f40bbfc0304
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M spi25_statusreg.c
1 file changed, 56 insertions(+), 70 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/28/59528/58
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#61).
Change subject: libflashrom,writeprotect: add flashrom_wp_get_available_ranges()
......................................................................
libflashrom,writeprotect: add flashrom_wp_get_available_ranges()
Generate list of available ranges by enumerating all possible values
that range bits (BPx, TB, ...) can take and using the chip's range
decoding function to get the range that is selected by each one.
BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom --wp-list
Change-Id: Id51f038f03305c8536d80313e52f77d27835f34d
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M libflashrom.c
M libflashrom.h
M writeprotect.c
M writeprotect.h
4 files changed, 281 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/81/58481/61
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I'd like you to reexamine a change. Please visit
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Change subject: writeprotect.h: add structure to represent chip wp configuration bits
......................................................................
writeprotect.h: add structure to represent chip wp configuration bits
Add `struct wp_bits` for representing values of all WP bits in a chip's
status/config register(s).
It allows most WP code to store and manipulate a chip's configuration
without knowing the exact layout of bits in the chip's status registers.
Supporting other chips may require additional fields to be added to the
structure.
BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
Change-Id: I17dee630248ce7b51e624a6e46d7097d5d0de809
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M writeprotect.h
1 file changed, 36 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/58478/42
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Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/58477 )
Change subject: flash.h,flashchips.c: add writeprotect bit layout map to chips
......................................................................
flash.h,flashchips.c: add writeprotect bit layout map to chips
This patch adds a register bit map `struct reg_bit_info`, with fields
for storing the register, bit index, and writability of each bit that
affects the chip's write protection. This allows writeprotect code to be
independent of the register layout of any specific chip. The new fields
have been filled out for example chips.
The representation is centered around describing how bits can be
accessed and modified, rather than the layout of registers. This is
generally easier to work with in code that needs to access specific bits
and typically requires specifying the locations of fewer bits overall.
BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
Change-Id: Id08d77e6d4ca5109c0d698271146d026dbc21284
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58477
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org>
---
M flash.h
M flashchips.c
M writeprotect.h
3 files changed, 77 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
Anastasia Klimchuk: Looks good to me, approved
diff --git a/flash.h b/flash.h
index cd40fa3..b935e9b 100644
--- a/flash.h
+++ b/flash.h
@@ -34,6 +34,7 @@
#include "libflashrom.h"
#include "layout.h"
+#include "writeprotect.h"
#define KiB (1024)
#define MiB (1024 * KiB)
@@ -176,6 +177,24 @@
MAX_REGISTERS
};
+struct reg_bit_info {
+ /* Register containing the bit */
+ enum flash_reg reg;
+
+ /* Bit index within register */
+ uint8_t bit_index;
+
+ /*
+ * Writability of the bit. RW does not guarantee the bit will be
+ * writable, for example if status register protection is enabled.
+ */
+ enum {
+ RO, /* Read only */
+ RW, /* Readable and writable */
+ OTP /* One-time programmable */
+ } writability;
+};
+
struct flashchip {
const char *vendor;
const char *name;
@@ -255,6 +274,37 @@
/* SPI specific options (TODO: Make it a union in case other bustypes get specific options.) */
uint8_t wrea_override; /**< override opcode for write extended address register */
+ struct reg_bit_map {
+ /* Status register protection bit (SRP) */
+ struct reg_bit_info srp;
+
+ /* Status register lock bit (SRP) */
+ struct reg_bit_info srl;
+
+ /*
+ * Note: some datasheets refer to configuration bits that
+ * function like TB/SEC/CMP bits as BP bits (e.g. BP3 for a bit
+ * that functions like TB).
+ *
+ * As a convention, any config bit that functions like a
+ * TB/SEC/CMP bit should be assigned to the respective
+ * tb/sec/cmp field in this structure, even if the datasheet
+ * uses a different name.
+ */
+
+ /* Block protection bits (BP) */
+ /* Extra element for terminator */
+ struct reg_bit_info bp[MAX_BP_BITS + 1];
+
+ /* Top/bottom protection bit (TB) */
+ struct reg_bit_info tb;
+
+ /* Sector/block protection bit (SEC) */
+ struct reg_bit_info sec;
+
+ /* Complement bit (CMP) */
+ struct reg_bit_info cmp;
+ } reg_bits;
};
typedef int (*chip_restore_fn_cb_t)(struct flashctx *flash, uint8_t status);
diff --git a/flashchips.c b/flashchips.c
index 9e10b5d..e12c8fc 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -6345,6 +6345,15 @@
.write = spi_chip_write_256,
.read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
.voltage = {1695, 1950},
+ .reg_bits =
+ {
+ .srp = {STATUS1, 7, RW},
+ .srl = {STATUS2, 0, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
+ .tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */
+ .sec = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */
+ .cmp = {STATUS2, 6, RW},
+ },
},
{
@@ -6744,6 +6753,13 @@
.write = spi_chip_write_256,
.read = spi_chip_read,
.voltage = {2700, 3600},
+ .reg_bits =
+ {
+ .srp = {STATUS1, 7, RW},
+ .srl = {STATUS2, 6, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
+ .tb = {STATUS1, 6, RW},
+ },
},
{
@@ -6783,6 +6799,15 @@
.write = spi_chip_write_256,
.read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
.voltage = {2700, 3600},
+ .reg_bits =
+ {
+ .srp = {STATUS1, 7, RW},
+ .srl = {STATUS2, 0, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
+ .tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */
+ .sec = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */
+ .cmp = {STATUS2, 6, RW},
+ },
},
{
diff --git a/writeprotect.h b/writeprotect.h
index 2d99897..8510226 100644
--- a/writeprotect.h
+++ b/writeprotect.h
@@ -18,4 +18,6 @@
#ifndef __WRITEPROTECT_H__
#define __WRITEPROTECT_H__ 1
+#define MAX_BP_BITS 4
+
#endif /* !__WRITEPROTECT_H__ */
36 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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