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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62480 )
Change subject: ft2232_spi.c: Add FTDI FT4233H
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> You're welcome ! Do you need something else to finish the Pull request ?
Everything fine. sometimes people are just slow to click. Thanks for the patch
and the reminder :)
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62251 )
Change subject: ichspi: Add Alder Lake support
......................................................................
Patch Set 13:
(3 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/62251/comment/396dfb6b_42153b0d
PS12, Line 12: TEST=```localhost ~ # flashrom --flash-name
> Thanks for that detail. […]
Added to commit message, thanks Sam for following up with the hardware!
Patchset:
PS12:
> So far I've seen no difference beside the number of straps in the descriptor.
Probably best to start with a new enum and collapse down as a optimisation patch as a follow up rather than prematurely. It looks like a large amount of enum optimisation could be had in the ich code in general so seems better to either do the entire refactor chain totally and not half baked WDYT?
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/62251/comment/984bff90_6fa6b3ca
PS12, Line 307: case CHIPSET_600_SERIES_ALDER_POINT:
> From the values available in the FIT tool, I think you're right.
Good spot, case was on the wrong line, It meant for it to be under 500, Fixed.
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Hello Sam McNally, build bot (Jenkins), Nico Huber, Subrata Banik, Rizwan Qureshi, Angel Pons, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/62251
to look at the new patch set (#13).
Change subject: ichspi: Add Alder Lake support
......................................................................
ichspi: Add Alder Lake support
Does exactly what it says on the tin.
BUG=b:220799648
TEST=```localhost ~ # flashrom --flash-name
<snip>
Found Programmer flash chip "Opaque flash chip" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000.
vendor="Programmer" name="Opaque flash chip"
flashrom -p internal --ifd -i fd -i bios -r /tmp/filename.rom
flashrom unknown on Linux 5.15.22 (x86_64)
flashrom is free software, get the source code at https://flashrom.org
Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
coreboot table found at 0x768a7000.
Found chipset "Intel Alder Lake-N".
Enabling flash write... Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed.
New value is 0x8b.
SPI Configuration is locked down.
OK.
Found Winbond flash chip "W25Q256JV_M" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000.
Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000
/dev/mem mmap failed: Resource temporarily unavailable
Could not map flash chip W25Q256JV_M at 0x00000000fe000000.
Reading ich descriptor... done.
Using regions: "bios", "fd".
Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000
/dev/mem mmap failed: Resource temporarily unavailable
Could not map flash chip W25Q256JV_M at 0x00000000fe000000.
Reading flash... done.
SUCCESS
Also,
Reading ich descriptor... Reading 4096 bytes starting at 0x000000.
done.
Assuming chipset '600 series Alder Point'.
Added layout entry 00000000 - 00000fff named fd
Added layout entry 00500000 - 01ffffff named bios
Added layout entry 00001000 - 004fffff named me
```
Tested on Nivviks/ADL-N and Brya/ADL-P.
Change-Id: Ie66cf519df13f3391c41f5016b16a81ef3dfd4bf
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M chipset_enable.c
M ich_descriptors.c
M ichspi.c
M programmer.h
M util/ich_descriptors_tool/ich_descriptors_tool.c
5 files changed, 34 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/51/62251/13
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Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62251 )
Change subject: ichspi: Add Alder Lake support
......................................................................
Patch Set 12:
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/62251/comment/f2e4b91c_1b362f84
PS12, Line 12: TEST=```localhost ~ # flashrom --flash-name
> > This tests the changes to `guess_ich_chipset_from_content()`, please check the flashrom log to ver […]
Thanks for that detail.
With Nivviks/ADL-N and Brya/ADL-P:
```
Reading ich descriptor... Reading 4096 bytes starting at 0x000000.
done.
Assuming chipset '600 series Alder Point'.
Added layout entry 00000000 - 00000fff named fd
Added layout entry 00500000 - 01ffffff named bios
Added layout entry 00001000 - 004fffff named me
```
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/62251/comment/eddcfd4c_5ad9d2ee
PS12, Line 307: case CHIPSET_600_SERIES_ALDER_POINT:
> Looking at the ADL-P SPI Guide Rev. 1.24, it shows the same numbers as […]
From the values available in the FIT tool, I think you're right.
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 )
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 13:
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/61854/comment/53800e7d_3c5ef805
PS7, Line 17: Without this synchronisation being implemented, flashrom is running
: into below error:
:
: Erasing and writing flash chip... Timeout error between offset
: 0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED!
: Uh oh. Erase/write failed. Checking if anything has changed.
> > > > Please let me know if anything we need to help for moving this CL?
> > >
> > > What was said in the first message of the comment thread.
> >
> > I have reattempted to update the commit msg with setup details and replication steps.
> >
> > Please suggest if you need better wordings.
>
> Ping!
Ping!
https://review.coreboot.org/c/flashrom/+/61854/comment/c92fbac5_a48a3a68
PS7, Line 25: TEST=Concurrent flashrom access is not throwing timeout.
> > > > Please let me know if anything we need to help for moving this CL?
> > >
> > > What was said in the first message of the comment thread.
> >
> > I'm able to verify this change on eve device. Updated the same in the commit msg.
>
> Ping!
Ping!
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