March 2022 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: writeprotect.c: refactor and fix wp_mode functions
by Nikolai Artemiev (Code Review) 07 Mar '22

07 Mar '22

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/62643 ) Change subject: writeprotect.c: refactor and fix wp_mode functions ...................................................................... writeprotect.c: refactor and fix wp_mode functions Use a lookup table in get_wp_mode() and drop the srp_bit_present check, since a chip without SRP is just FLASHROM_WP_MODE_DISABLED. Add a srp_bit_present check to set_wp_mode() if the mode requires it. BUG=b:182223106 BRANCH=none TEST=builds Change-Id: Ib6c347453f9216e5816e4ed35bf9783fd3c720e0 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M writeprotect.c 1 file changed, 13 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/43/62643/1 diff --git a/writeprotect.c b/writeprotect.c index 6b3bbcf..5893593 100644 --- a/writeprotect.c +++ b/writeprotect.c @@ -351,16 +351,17 @@ /** Get the mode selected by a WP configuration. */ static int get_wp_mode(enum flashrom_wp_mode *mode, const struct wp_bits *bits) { - if (!bits->srp_bit_present) - return FLASHROM_WP_ERR_CHIP_UNSUPPORTED; + const enum flashrom_wp_mode wp_modes[2][2] = { + { + FLASHROM_WP_MODE_DISABLED, /* srl=0, srp=0 */ + FLASHROM_WP_MODE_HARDWARE, /* srl=0, srp=1 */ + }, { + FLASHROM_WP_MODE_POWER_CYCLE, /* srl=1, srp=0 */ + FLASHROM_WP_MODE_PERMANENT, /* srl=1, srp=1 */ + }, + }; - if (bits->srl_bit_present && bits->srl == 1) { - *mode = bits->srp ? FLASHROM_WP_MODE_PERMANENT : - FLASHROM_WP_MODE_POWER_CYCLE; - } else { - *mode = bits->srp ? FLASHROM_WP_MODE_HARDWARE : - FLASHROM_WP_MODE_DISABLED; - } + *mode = wp_modes[bits->srl][bits->srp]; return FLASHROM_WP_OK; } @@ -375,6 +376,9 @@ return FLASHROM_WP_OK; case FLASHROM_WP_MODE_HARDWARE: + if (!bits->srp_bit_present) + return FLASHROM_WP_ERR_CHIP_UNSUPPORTED; + bits->srl = 0; bits->srp = 1; return FLASHROM_WP_OK; -- To view, visit https://review.coreboot.org/c/flashrom/+/62643 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib6c347453f9216e5816e4ed35bf9783fd3c720e0 Gerrit-Change-Number: 62643 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
by Subrata Banik (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Patrick Georgi, Stefan Reinauer, Angel Pons, Sridhar Siricilla, Alex Levin, YH Lin, Nico Huber, Martin Roth, Caveh Jalali, David Hendricks, Tim Wawrzynczak, Nick Vaccaro, Boris Mittelberg. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 ) Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq ...................................................................... Patch Set 14: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/61854/comment/7c173d79_ee3aa327 PS7, Line 25: TEST=Concurrent flashrom access is not throwing timeout. > Eve was tested which is the Kabylake-Y uarch, navigating the Intel marketing matrix here but that comes out as a 100 series pch to me so more or less ich9 in older terminology. I think that is the oldest we are able to locally test. > > Seems resolved AFAIK. Although do reach out on the IRC channel Subrata if at all possible just in case someone happens to have something extremely old available. > > I will ping damo22 out of band who happens to have some very old Intel stuff. Thanks Edward, I will also check over IRC if someone can help. Please do let me know if you could manage to get some volunteer for additional checking. -- To view, visit https://review.coreboot.org/c/flashrom/+/61854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484 Gerrit-Change-Number: 61854 Gerrit-PatchSet: 14 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Alex Levin <levinale(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Damien Zammit Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Alex Levin <levinale(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 11:09:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: David Hendricks <david.hendricks(a)gmail.com> Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
by Edward O'Callaghan (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Patrick Georgi, Stefan Reinauer, Angel Pons, Sridhar Siricilla, Alex Levin, YH Lin, Nico Huber, Martin Roth, Subrata Banik, Caveh Jalali, David Hendricks, Tim Wawrzynczak, Nick Vaccaro, Boris Mittelberg. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 ) Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq ...................................................................... Patch Set 14: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/61854/comment/622ccce1_999f062b PS7, Line 25: TEST=Concurrent flashrom access is not throwing timeout. > > > > > > Please let me know if anything we need to help for moving this CL? […] Eve was tested which is the Kabylake-Y uarch, navigating the Intel marketing matrix here but that comes out as a 100 series pch to me so more or less ich9 in older terminology. I think that is the oldest we are able to locally test. Seems resolved AFAIK. Although do reach out on the IRC channel Subrata if at all possible just in case someone happens to have something extremely old available. I will ping damo22 out of band who happens to have some very old Intel stuff. -- To view, visit https://review.coreboot.org/c/flashrom/+/61854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484 Gerrit-Change-Number: 61854 Gerrit-PatchSet: 14 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Alex Levin <levinale(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Damien Zammit Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Alex Levin <levinale(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 10:45:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: comment

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Change in flashrom[master]: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
by Subrata Banik (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Patrick Georgi, Stefan Reinauer, Angel Pons, Sridhar Siricilla, Alex Levin, YH Lin, Nico Huber, Martin Roth, Subrata Banik, Caveh Jalali, David Hendricks, Tim Wawrzynczak, Nick Vaccaro, Boris Mittelberg. Hello build bot (Jenkins), Patrick Georgi, Rizwan Qureshi, Stefan Reinauer, Angel Pons, Sridhar Siricilla, Alex Levin, YH Lin, Nico Huber, Martin Roth, Caveh Jalali, Tim Wawrzynczak, Edward O'Callaghan, Nick Vaccaro, Boris Mittelberg, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/61854 to look at the new patch set (#14). Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq ...................................................................... ichspi.c: Check SPI Cycle In-Progress prior start HW Seq As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. This bit remains set until the cycle completes on the SPI interface. Hardware automatically sets and clears this bit. Software must initiate the next SPI transaction when this bit is 0. Platform Setup: Alder Lake based ChromeOS devices (Brya variants) Replication Steps: Accepting and running firmware Auto Update (AU) on the Brya variants (dogfooder system) is seeing `flashrom` getting timed out. Problem Statement: Evidencing AU (Auto Update) failure while performing firmware update on the Alder Lake based ChromeOS devices. Observation: Based on the initial understanding from the failure log/pattern, it seems like the platform is evidencing multiple `flashrom` access from different source, for example: `futility` accesses flashrom for erase, write and read operation, `crossystem` uses flashrom for updating VBNV, additionally, `set_fw_good` script also uses `crossystem` to update the fw status. Solution: Without this SCIP check being implemented in flashrom, there is no way to ensure multiple instances of flashrom performing different SPI operations are not cancelling each other and running into below error: Erasing and writing flash chip... Timeout error between offset 0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED! Uh oh. Erase/write failed. Checking if anything has changed. TEST=Able to flash coreboot image on Alder Lake, Brya variants, Tiger Lake, Volteer variants, Kaby Lake, Eve system and Comet Lake, Hatch variants without any failure. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484 --- M ichspi.c 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/61854/14 -- To view, visit https://review.coreboot.org/c/flashrom/+/61854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484 Gerrit-Change-Number: 61854 Gerrit-PatchSet: 14 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Alex Levin <levinale(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Alex Levin <levinale(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
by Edward O'Callaghan (Code Review) 06 Mar '22

06 Mar '22

Attention is currently required from: Patrick Georgi, Stefan Reinauer, Angel Pons, Sridhar Siricilla, Alex Levin, YH Lin, Nico Huber, Martin Roth, Subrata Banik, Caveh Jalali, David Hendricks, Tim Wawrzynczak, Nick Vaccaro, Boris Mittelberg. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 ) Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq ...................................................................... Patch Set 13: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/61854/comment/2868861a_cfd68c9a PS7, Line 17: Without this synchronisation being implemented, flashrom is running : into below error: : : Erasing and writing flash chip... Timeout error between offset : 0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED! : Uh oh. Erase/write failed. Checking if anything has changed. > > > > > > Please let me know if anything we need to help for moving this CL? […] ACK. This seems resolved based on my latest reading of the commit message. -- To view, visit https://review.coreboot.org/c/flashrom/+/61854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484 Gerrit-Change-Number: 61854 Gerrit-PatchSet: 13 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Alex Levin <levinale(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Alex Levin <levinale(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 01:47:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in flashrom[master]: ichspi: Add Alder Lake support
by Edward O'Callaghan (Code Review) 06 Mar '22

06 Mar '22

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62251 ) Change subject: ichspi: Add Alder Lake support ...................................................................... ichspi: Add Alder Lake support Does exactly what it says on the tin. BUG=b:220799648 TEST=```localhost ~ # flashrom --flash-name <snip> Found Programmer flash chip "Opaque flash chip" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000. vendor="Programmer" name="Opaque flash chip" flashrom -p internal --ifd -i fd -i bios -r /tmp/filename.rom flashrom unknown on Linux 5.15.22 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). coreboot table found at 0x768a7000. Found chipset "Intel Alder Lake-N". Enabling flash write... Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed. New value is 0x8b. SPI Configuration is locked down. OK. Found Winbond flash chip "W25Q256JV_M" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000 /dev/mem mmap failed: Resource temporarily unavailable Could not map flash chip W25Q256JV_M at 0x00000000fe000000. Reading ich descriptor... done. Using regions: "bios", "fd". Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000 /dev/mem mmap failed: Resource temporarily unavailable Could not map flash chip W25Q256JV_M at 0x00000000fe000000. Reading flash... done. SUCCESS Also, Reading ich descriptor... Reading 4096 bytes starting at 0x000000. done. Assuming chipset '600 series Alder Point'. Added layout entry 00000000 - 00000fff named fd Added layout entry 00500000 - 01ffffff named bios Added layout entry 00001000 - 004fffff named me ``` Tested on Nivviks/ADL-N and Brya/ADL-P. Change-Id: Ie66cf519df13f3391c41f5016b16a81ef3dfd4bf Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62251 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Sam McNally <sammc(a)google.com> --- M chipset_enable.c M ich_descriptors.c M ichspi.c M programmer.h M util/ich_descriptors_tool/ich_descriptors_tool.c 5 files changed, 34 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Sam McNally: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/chipset_enable.c b/chipset_enable.c index d4285a5..ac9377b 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -605,6 +605,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_ELKHART_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: @@ -709,6 +710,7 @@ boot_straps = boot_straps_pch8_lp; break; case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_600_SERIES_ALDER_POINT: boot_straps = boot_straps_pch500; break; case CHIPSET_APOLLO_LAKE: @@ -741,6 +743,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: @@ -994,6 +997,11 @@ return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_500_SERIES_TIGER_POINT); } +static int enable_flash_pch600(struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_600_SERIES_ALDER_POINT); +} + static int enable_flash_mcc(struct pci_dev *const dev, const char *const name) { return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_ELKHART_LAKE); @@ -2141,6 +2149,8 @@ {0x8086, 0x4389, B_S, NT, "Intel", "WM590", enable_flash_pch500}, {0x8086, 0x438a, B_S, NT, "Intel", "QM580", enable_flash_pch500}, {0x8086, 0x438b, B_S, DEP, "Intel", "HM570", enable_flash_pch500}, + {0x8086, 0x54a4, B_S, DEP, "Intel", "Alder Lake-N", enable_flash_pch600}, + {0x8086, 0x51a4, B_S, DEP, "Intel", "Alder Lake-P", enable_flash_pch600}, #endif {0}, }; diff --git a/ich_descriptors.c b/ich_descriptors.c index 0ce5720..256224d 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -46,6 +46,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_ELKHART_LAKE: return 16; case CHIPSET_100_SERIES_SUNRISE_POINT: @@ -72,6 +73,7 @@ switch (cs) { case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_APOLLO_LAKE: + case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: if (cont->NM <= MAX_NUM_MASTERS) @@ -111,7 +113,7 @@ "8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg", "9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point", "C620 series Lewisburg", "300 series Cannon Point", "400 series Comet Point", - "500 series Tiger Point", "Apollo Lake", "Gemini Lake", "Elkhart Lake", + "500 series Tiger Point", "600 series Alder Point", "Apollo Lake", "Gemini Lake", "Elkhart Lake", }; if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names)) cs = 0; @@ -206,6 +208,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: { @@ -300,6 +303,7 @@ case CHIPSET_GEMINI_LAKE: return freq_str[2][value]; case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_600_SERIES_ALDER_POINT: return freq_str[3][value]; case CHIPSET_ELKHART_LAKE: return freq_str[4][value]; @@ -346,6 +350,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: @@ -470,7 +475,8 @@ if (cs == CHIPSET_100_SERIES_SUNRISE_POINT || cs == CHIPSET_300_SERIES_CANNON_POINT || cs == CHIPSET_400_SERIES_COMET_POINT || - cs == CHIPSET_500_SERIES_TIGER_POINT) { + cs == CHIPSET_500_SERIES_TIGER_POINT || + cs == CHIPSET_600_SERIES_ALDER_POINT) { const char *const master_names[] = { "BIOS", "ME", "GbE", "unknown", "EC", }; @@ -1031,6 +1037,8 @@ return CHIPSET_300_SERIES_CANNON_POINT; if (content->CSSL == 0x11) return CHIPSET_500_SERIES_TIGER_POINT; + if (content->CSSL == 0x14) + return CHIPSET_600_SERIES_ALDER_POINT; if (content->CSSL == 0x03) return CHIPSET_ELKHART_LAKE; msg_pwarn("Unknown flash descriptor, assuming 500 series compatibility.\n"); @@ -1054,6 +1062,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: /* `freq_read` was repurposed, so can't check on it any more. */ @@ -1210,6 +1219,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: @@ -1249,6 +1259,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: diff --git a/ichspi.c b/ichspi.c index 117ff8d..84ac035 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1781,6 +1781,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: @@ -1817,6 +1818,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: @@ -1875,6 +1877,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: @@ -1952,6 +1955,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_BAYTRAIL: @@ -1988,6 +1992,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: @@ -2022,7 +2027,8 @@ (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT || ich_gen == CHIPSET_300_SERIES_CANNON_POINT || ich_gen == CHIPSET_400_SERIES_COMET_POINT || - ich_gen == CHIPSET_500_SERIES_TIGER_POINT)) { + ich_gen == CHIPSET_500_SERIES_TIGER_POINT || + ich_gen == CHIPSET_600_SERIES_ALDER_POINT)) { msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n"); ich_spi_mode = ich_hwseq; } diff --git a/programmer.h b/programmer.h index 9305afb..6a0c3fa 100644 --- a/programmer.h +++ b/programmer.h @@ -353,6 +353,7 @@ CHIPSET_300_SERIES_CANNON_POINT, CHIPSET_400_SERIES_COMET_POINT, CHIPSET_500_SERIES_TIGER_POINT, + CHIPSET_600_SERIES_ALDER_POINT, CHIPSET_APOLLO_LAKE, CHIPSET_GEMINI_LAKE, CHIPSET_ELKHART_LAKE, diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index f743510..532a1fb 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -137,6 +137,7 @@ "\t- \"300\" or \"cannon\" for Intel's 300 series chipsets.\n" "\t- \"400\" or \"comet\" for Intel's 400 series chipsets.\n" "\t- \"500\" or \"tiger\" for Intel's 500 series chipsets.\n" +"\t- \"600\" or \"alder\" for Intel's 600 series chipsets.\n" "If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n" "the GbE blob that is required to initialize the GbE are also dumped to files.\n", argv[0], argv[0]); @@ -234,6 +235,8 @@ else if ((strcmp(csn, "500") == 0) || (strcmp(csn, "tiger") == 0)) cs = CHIPSET_500_SERIES_TIGER_POINT; + else if (strcmp(csn, "600") == 0) + cs = CHIPSET_600_SERIES_ALDER_POINT; else if (strcmp(csn, "apollo") == 0) cs = CHIPSET_APOLLO_LAKE; else if (strcmp(csn, "gemini") == 0) -- To view, visit https://review.coreboot.org/c/flashrom/+/62251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie66cf519df13f3391c41f5016b16a81ef3dfd4bf Gerrit-Change-Number: 62251 Gerrit-PatchSet: 15 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: merged

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Change in flashrom[1.1.x]: test_build.sh: Move build test procedure to repository
by Edward O'Callaghan (Code Review) 06 Mar '22

06 Mar '22

Attention is currently required from: Nico Huber, Patrick Georgi. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62617 ) Change subject: test_build.sh: Move build test procedure to repository ...................................................................... Patch Set 1: (1 comment) File test_build.sh: https://review.coreboot.org/c/flashrom/+/62617/comment/7c08c210_9b1a4086 PS1, Line 5: > This is just a backport to a release branch to allow changes there to pass […] Ack. Just wanted to get the idea across. -- To view, visit https://review.coreboot.org/c/flashrom/+/62617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.1.x Gerrit-Change-Id: I37a8e925d1b283c3b8f87cb3d0f1ed8920f2cf95 Gerrit-Change-Number: 62617 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Comment-Date: Mon, 07 Mar 2022 00:08:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[1.1.x]: test_build.sh: Move build test procedure to repository
by Nico Huber (Code Review) 06 Mar '22

06 Mar '22

Attention is currently required from: Patrick Georgi, Edward O'Callaghan. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62617 ) Change subject: test_build.sh: Move build test procedure to repository ...................................................................... Patch Set 1: (1 comment) File test_build.sh: https://review.coreboot.org/c/flashrom/+/62617/comment/b4e0a99c_cac9c67a PS1, Line 5: > should a make install step also be attempted into somewhere prefixed into /tmp ? This is just a backport to a release branch to allow changes there to pass today's Jenkins setup. Generaly, a good idea to test more make targets. -- To view, visit https://review.coreboot.org/c/flashrom/+/62617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.1.x Gerrit-Change-Id: I37a8e925d1b283c3b8f87cb3d0f1ed8920f2cf95 Gerrit-Change-Number: 62617 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Sun, 06 Mar 2022 12:24:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[1.1.x]: test_build.sh: Move build test procedure to repository
by Edward O'Callaghan (Code Review) 06 Mar '22

06 Mar '22

Attention is currently required from: Nico Huber, Patrick Georgi. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62617 ) Change subject: test_build.sh: Move build test procedure to repository ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File test_build.sh: https://review.coreboot.org/c/flashrom/+/62617/comment/592d682f_58fbbfa9 PS1, Line 5: should a make install step also be attempted into somewhere prefixed into /tmp ? -- To view, visit https://review.coreboot.org/c/flashrom/+/62617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.1.x Gerrit-Change-Id: I37a8e925d1b283c3b8f87cb3d0f1ed8920f2cf95 Gerrit-Change-Number: 62617 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Comment-Date: Sun, 06 Mar 2022 09:31:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[1.1.x]: dmi: Correctly check for ERROR_PTR
by Edward O'Callaghan (Code Review) 06 Mar '22

06 Mar '22

Attention is currently required from: Nico Huber, Angel Pons. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62613 ) Change subject: dmi: Correctly check for ERROR_PTR ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/62613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.1.x Gerrit-Change-Id: Ic403c2940c2b91acbd113f0acfa3ce9ef6c6bb6c Gerrit-Change-Number: 62613 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 06 Mar 2022 09:29:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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