March 2022 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: flashchips.c: add writeprotect support for more chips
by Edward O'Callaghan (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Nikolai Artemiev, Anastasia Klimchuk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62214 ) Change subject: flashchips.c: add writeprotect support for more chips ...................................................................... Patch Set 22: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/62214/comment/9ae0b81d_ba66a9ff PS22, Line 9: Chip(s) tested which masters were used during the testing? -- To view, visit https://review.coreboot.org/c/flashrom/+/62214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7f3d4c4148056098a845b5c64308b0333ebda395 Gerrit-Change-Number: 62214 Gerrit-PatchSet: 22 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 02:46:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: flashchips.c: add writeprotect support for more chips
by Edward O'Callaghan (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Nikolai Artemiev, Anastasia Klimchuk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62214 ) Change subject: flashchips.c: add writeprotect support for more chips ...................................................................... Patch Set 22: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/62214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7f3d4c4148056098a845b5c64308b0333ebda395 Gerrit-Change-Number: 62214 Gerrit-PatchSet: 22 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 02:46:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: cli_classic: add writeprotect CLI
by Edward O'Callaghan (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Nico Huber, Paul Menzel, Angel Pons, Nikolai Artemiev, Sergii Dmytruk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58738 ) Change subject: cli_classic: add writeprotect CLI ...................................................................... Patch Set 68: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/58738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I499f521781ee8999921996517802c0c0c641d869 Gerrit-Change-Number: 58738 Gerrit-PatchSet: 68 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 02:43:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
by Damien Zammit (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Patrick Georgi, Stefan Reinauer, Angel Pons, Sridhar Siricilla, Alex Levin, YH Lin, Nico Huber, Martin Roth, Subrata Banik, Caveh Jalali, David Hendricks, Tim Wawrzynczak, Nick Vaccaro, Boris Mittelberg. Damien Zammit has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 ) Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq ...................................................................... Patch Set 14: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/61854/comment/5c6c58a3_02c833e0 PS7, Line 25: TEST=Concurrent flashrom access is not throwing timeout. > > Eve was tested which is the Kabylake-Y uarch, navigating the Intel marketing matrix here but that […] I just tested this with Lenovo W530 (Ivybridge). I was able to read the bios region using a layout. ``` * 1efdc43 (HEAD) ichspi.c: Check SPI Cycle In-Progress prior start HW Seq | * 6289508 (origin/master, master) pcidev: Move scandev_inclass logic from internal to pcidev | * bc2e3b6 ft2232_spi.c: Add FTDI FT4233H | * 00194ea pcidev: Move pci_get_dev() logic into canonical place | * 12dbc4e writeprotect: add {get,set}_wp_mode() | * 4cb8464 writeprotect: add set_wp_range() | * a548fe5 libflashrom,writeprotect: add flashrom_wp_get_available_ranges() | * 2c3a2d6 writeprotect: add get_wp_range() for decoding ranges | * 9fc100f flashchips,writeprotect_ranges: add range decoding function | * cff87a8 libflashrom,writeprotect: add functions for reading/writing WP configs | * 645e5e7 writeprotect.h: add structure to represent chip wp configuration bits | * e007908 flash.h,flashchips.c: add writeprotect bit layout map to chips |/ * b7ea3a9 spi25_statusreg,flashchips: add SR2 read/write support ``` [damien@zamlap flashrom]$ sudo ./flashrom -pinternal -V --noverify-all --layout ~/w530/layout --image bios -r ~/test.rom flashrom v1.2-629-g1efdc43 on Linux 4.18.0-305.10.2.el8_4.x86_64 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). flashrom was built with unknown PCI library, GCC 8.4.1 20200928 (Red Hat 8.4.1-1), little endian Command line (9 args): ./flashrom -pinternal -V --noverify-all --layout /home/damien/w530/layout --image bios -r /home/damien/test.rom Added layout entry 00000000 - 00000fff named fd Added layout entry 00500000 - 00bfffff named bios Added layout entry 00003000 - 004fffff named me Added layout entry 00001000 - 00002fff named gbe Using region: "bios". Initializing internal programmer /sys/class/mtd/mtd0 does not exist Found candidate at: 00000500-00000528 Found coreboot table at 0x00000500. Found candidate at: 00000000-00000c2c Found coreboot table at 0x00000000. coreboot table found at 0x7ff62000. coreboot header(24) checksum: 19b0 table(3092) checksum: 486c entries: 34 Vendor ID: LENOVO, part ID: ThinkPad W530 Using Internal DMI decoder. DMI string chassis-type: "Laptop" Laptop detected via DMI. DMI string system-manufacturer: "LENOVO" DMI string system-product-name: "24384ZU" DMI string system-version: "ThinkPad W530" DMI string baseboard-manufacturer: "LENOVO" DMI string baseboard-product-name: "24384ZU" DMI string baseboard-version: "ThinkPad W530" W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 00. Found chipset "Intel QM77" with PCI ID 8086:1e55. Enabling flash write... Root Complex Register Block address = 0xfed1c000 GCS = 0xc21: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) Top Swap: not enabled 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x4 0x7fffffff/0x7fffffff FWH IDSEL: 0x5 0x7fffffff/0x7fffffff FWH IDSEL: 0x6 0x7fffffff/0x7fffffff FWH IDSEL: 0x7 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled Maximum FWH chip size: 0x100000 bytes SPI Read Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled SPIBAR = 0x00007f1ad053d000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 SPI Configuration is locked down. Reading OPCODES... done 0x06: 0x3f00 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x0bff0500 FREG1: BIOS region (0x00500000-0x00bfffff) is read-write. 0x5C: 0x04ff0003 FREG2: Management Engine region (0x00003000-0x004fffff) is locked. 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write. Not all flash regions are freely accessible by flashrom. This is most likely due to an active ME. Please see https://flashrom.org/ME for details. At least some flash regions are read protected. You have to use a flash layout and include only accessible regions. For write operations, you'll additionally need the --noverify-all switch. See manpage for more details. 0x90: 0xc0 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0x91: 0xf90000 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=1 0x94: 0x5006 (PREOP) 0x96: 0xb32d (OPTYPE) 0x98: 0x05030201 (OPMENU) 0x9c: 0x0bd89f20 (OPMENU+4) 0xa0: 0x00000000 (BBAR) 0xc4: 0x00802005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xc8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 0xd0: 0x00000000 (FPB) Enabling hardware sequencing due to multiple flash chips detected. OK. The following protocols are supported: Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Hardware sequencing reports 2 attached SPI flash chips with a combined density of 12288 kB. Added layout entry 00000000 - 00bfffff named complete flash Found Programmer flash chip "Opaque flash chip" (12288 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Found Programmer flash chip "Opaque flash chip" (12288 kB, Programmer-specific). Reading flash... Reading 7340032 bytes starting at 0x500000. done. Restoring MMIO space at 0x7f1ad05408a0 $ Patchset: PS14: Works on my end. -- To view, visit https://review.coreboot.org/c/flashrom/+/61854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484 Gerrit-Change-Number: 61854 Gerrit-PatchSet: 14 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Alex Levin <levinale(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Alex Levin <levinale(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Mon, 07 Mar 2022 23:46:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: David Hendricks <david.hendricks(a)gmail.com> Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[1.0.x]: tree: Make internal variables static
by Nico Huber (Code Review) 07 Mar '22

07 Mar '22

Attention is currently required from: Jacob Garber. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62615 ) Change subject: tree: Make internal variables static ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Patchset: PS1: Given that the parent passed Jenkins, it seems we don't need this commit on the 1.0.x branch. I'll have a second look if it fixes anything. Until then, sorry for the noise. -- To view, visit https://review.coreboot.org/c/flashrom/+/62615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.0.x Gerrit-Change-Id: I1e55138adef540e9d3a2237aa5b289cb338c0608 Gerrit-Change-Number: 62615 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Comment-Date: Mon, 07 Mar 2022 16:48:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[1.0.x]: dmi: Correctly check for ERROR_PTR
by Nico Huber (Code Review) 07 Mar '22

07 Mar '22

Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62616 ) Change subject: dmi: Correctly check for ERROR_PTR ...................................................................... dmi: Correctly check for ERROR_PTR For the physmap*() functions, NULL is considered valid return value. Fixes a segmentation fault when DMI tables can't be mapped. Tested on intel/eblake board with broken coreboot. Change-Id: Ic403c2940c2b91acbd113f0acfa3ce9ef6c6bb6c Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62616 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M dmi.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/dmi.c b/dmi.c index 729cdb1..2d17294 100644 --- a/dmi.c +++ b/dmi.c @@ -169,7 +169,7 @@ int i = 0, j = 0; uint8_t *dmi_table_mem = physmap_ro("DMI Table", base, len); - if (dmi_table_mem == NULL) { + if (dmi_table_mem == ERROR_PTR) { msg_perr("Unable to access DMI Table\n"); return; } -- To view, visit https://review.coreboot.org/c/flashrom/+/62616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.0.x Gerrit-Change-Id: Ic403c2940c2b91acbd113f0acfa3ce9ef6c6bb6c Gerrit-Change-Number: 62616 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in flashrom[1.0.x]: test_build.sh: Move build test procedure to repository
by Nico Huber (Code Review) 07 Mar '22

07 Mar '22

Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62614 ) Change subject: test_build.sh: Move build test procedure to repository ...................................................................... test_build.sh: Move build test procedure to repository Instead of hard coding the test procedure on qa.coreboot.org, allow running a script in the repo instead. The server is already adapted to do that, so once there's a test_build.sh file in the toplevel directory, it's run in place of the default operation. The content of this change mirrors the default operation exactly so should serve as a good starting point. The script is executed in an encapsulate[0] context with the workspace, /tmp and $HOME/.ccache writable, everything else read-only and network disabled. It should return 0 on success, anything else on failure, as is normal for UNIX processes. [0] https://review.coreboot.org/cgit/encapsulate.git (Backported minus the Meson support) Change-Id: I37a8e925d1b283c3b8f87cb3d0f1ed8920f2cf95 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46894 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62614 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- A test_build.sh 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/test_build.sh b/test_build.sh new file mode 100755 index 0000000..3ab5319 --- /dev/null +++ b/test_build.sh @@ -0,0 +1,4 @@ +#!/bin/sh +set -e + +make CONFIG_EVERYTHING=yes WARNERROR=yes -- To view, visit https://review.coreboot.org/c/flashrom/+/62614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.0.x Gerrit-Change-Id: I37a8e925d1b283c3b8f87cb3d0f1ed8920f2cf95 Gerrit-Change-Number: 62614 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in flashrom[1.1.x]: dmi: Correctly check for ERROR_PTR
by Nico Huber (Code Review) 07 Mar '22

07 Mar '22

Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62613 ) Change subject: dmi: Correctly check for ERROR_PTR ...................................................................... dmi: Correctly check for ERROR_PTR For the physmap*() functions, NULL is considered valid return value. Fixes a segmentation fault when DMI tables can't be mapped. Tested on intel/eblake board with broken coreboot. Change-Id: Ic403c2940c2b91acbd113f0acfa3ce9ef6c6bb6c Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62613 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M dmi.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved diff --git a/dmi.c b/dmi.c index 79321ce..cea07f8 100644 --- a/dmi.c +++ b/dmi.c @@ -164,7 +164,7 @@ int i = 0, j = 0; uint8_t *dmi_table_mem = physmap_ro("DMI Table", base, len); - if (dmi_table_mem == NULL) { + if (dmi_table_mem == ERROR_PTR) { msg_perr("Unable to access DMI Table\n"); return; } -- To view, visit https://review.coreboot.org/c/flashrom/+/62613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.1.x Gerrit-Change-Id: Ic403c2940c2b91acbd113f0acfa3ce9ef6c6bb6c Gerrit-Change-Number: 62613 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in flashrom[1.1.x]: tree: Make internal variables static
by Nico Huber (Code Review) 07 Mar '22

07 Mar '22

Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62612 ) Change subject: tree: Make internal variables static ...................................................................... tree: Make internal variables static All these variables are only used in the files they are defined in, so they can be made static. (Backported as it untangles aliased global objects.) Change-Id: I1e55138adef540e9d3a2237aa5b289cb338c0608 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33747 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62612 Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M dediprog.c M developerbox_spi.c M dummyflasher.c M gfxnvidia.c M it85spi.c M layout.c M mcp6x_spi.c M nicintel.c M nicintel_spi.c M satamv.c 10 files changed, 18 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved diff --git a/dediprog.c b/dediprog.c index c99c922..9379773 100644 --- a/dediprog.c +++ b/dediprog.c @@ -43,7 +43,7 @@ #define REQTYPE_OTHER_IN (LIBUSB_ENDPOINT_IN | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_OTHER) /* 0xC3 */ #define REQTYPE_EP_OUT (LIBUSB_ENDPOINT_OUT | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_ENDPOINT) /* 0x42 */ #define REQTYPE_EP_IN (LIBUSB_ENDPOINT_IN | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_ENDPOINT) /* 0xC2 */ -struct libusb_context *usb_ctx; +static struct libusb_context *usb_ctx; static libusb_device_handle *dediprog_handle; static int dediprog_in_endpoint; static int dediprog_out_endpoint; @@ -159,7 +159,7 @@ }; static int dediprog_firmwareversion = FIRMWARE_VERSION(0, 0, 0); -enum dediprog_devtype dediprog_devicetype = DEV_UNKNOWN; +static enum dediprog_devtype dediprog_devicetype = DEV_UNKNOWN; #if defined(LIBUSB_MAJOR) && defined(LIBUSB_MINOR) && defined(LIBUSB_MICRO) && \ LIBUSB_MAJOR <= 1 && LIBUSB_MINOR == 0 && LIBUSB_MICRO < 9 diff --git a/developerbox_spi.c b/developerbox_spi.c index 4ad966e..46da80e 100644 --- a/developerbox_spi.c +++ b/developerbox_spi.c @@ -60,7 +60,7 @@ {0}, }; -struct libusb_context *usb_ctx; +static struct libusb_context *usb_ctx; static libusb_device_handle *cp210x_handle; static int cp210x_gpio_get(void) diff --git a/dummyflasher.c b/dummyflasher.c index 2929686..53801d9 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -55,10 +55,10 @@ static unsigned int emu_jedec_be_d8_size = 0; static unsigned int emu_jedec_ce_60_size = 0; static unsigned int emu_jedec_ce_c7_size = 0; -unsigned char spi_blacklist[256]; -unsigned char spi_ignorelist[256]; -int spi_blacklist_size = 0; -int spi_ignorelist_size = 0; +static unsigned char spi_blacklist[256]; +static unsigned char spi_ignorelist[256]; +static int spi_blacklist_size = 0; +static int spi_ignorelist_size = 0; static uint8_t emu_status = 0; /* A legit complete SFDP table based on the MX25L6436E (rev. 1.8) datasheet. */ @@ -128,7 +128,7 @@ .chip_writen = dummy_chip_writen, }; -enum chipbustype dummy_buses_supported = BUS_NONE; +static enum chipbustype dummy_buses_supported = BUS_NONE; static int dummy_shutdown(void *data) { diff --git a/gfxnvidia.c b/gfxnvidia.c index c6d752e..d8ea4d6 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -28,7 +28,7 @@ #define GFXNVIDIA_MEMMAP_MASK ((1 << 17) - 1) #define GFXNVIDIA_MEMMAP_SIZE (16 * 1024 * 1024) -uint8_t *nvidia_bar; +static uint8_t *nvidia_bar; const struct dev_entry gfx_nvidia[] = { {0x10de, 0x0010, NT, "NVIDIA", "Mutara V08 [NV2]" }, diff --git a/it85spi.c b/it85spi.c index e47cabb..b616a26 100644 --- a/it85spi.c +++ b/it85spi.c @@ -74,9 +74,9 @@ #endif /* LPC_IO */ #ifdef LPC_IO -unsigned int shm_io_base; +static unsigned int shm_io_base; #endif -unsigned char *ce_high, *ce_low; +static unsigned char *ce_high, *ce_low; static int it85xx_scratch_rom_reenter = 0; /* This function will poll the keyboard status register until either diff --git a/layout.c b/layout.c index 5080e3e..96434e6 100644 --- a/layout.c +++ b/layout.c @@ -23,7 +23,7 @@ #include "programmer.h" #include "layout.h" -struct romentry entries[MAX_ROMLAYOUT]; +static struct romentry entries[MAX_ROMLAYOUT]; static struct flashrom_layout layout = { entries, 0 }; /* include_args holds the arguments specified at the command line with -i. They must be processed at some point diff --git a/mcp6x_spi.c b/mcp6x_spi.c index 971780d..d7dbdf0 100644 --- a/mcp6x_spi.c +++ b/mcp6x_spi.c @@ -36,7 +36,7 @@ #define MCP6X_SPI_REQUEST 0 #define MCP6X_SPI_GRANT 8 -void *mcp6x_spibar = NULL; +static void *mcp6x_spibar = NULL; /* Cached value of last GPIO state. */ static uint8_t mcp_gpiostate; diff --git a/nicintel.c b/nicintel.c index a4424e7..4672890 100644 --- a/nicintel.c +++ b/nicintel.c @@ -20,8 +20,8 @@ #include "programmer.h" #include "hwaccess.h" -uint8_t *nicintel_bar; -uint8_t *nicintel_control_bar; +static uint8_t *nicintel_bar; +static uint8_t *nicintel_control_bar; const struct dev_entry nics_intel[] = { {PCI_VENDOR_ID_INTEL, 0x1209, NT, "Intel", "8255xER/82551IT Fast Ethernet Controller"}, diff --git a/nicintel_spi.c b/nicintel_spi.c index f31a2f9..f5c9ed1 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -75,7 +75,7 @@ #define BIT(x) (1<<(x)) -uint8_t *nicintel_spibar; +static uint8_t *nicintel_spibar; const struct dev_entry nics_intel_spi[] = { {PCI_VENDOR_ID_INTEL, 0x105e, OK, "Intel", "82571EB Gigabit Ethernet Controller"}, diff --git a/satamv.c b/satamv.c index 1d3734a..31265ea 100644 --- a/satamv.c +++ b/satamv.c @@ -22,8 +22,8 @@ #include "programmer.h" #include "hwaccess.h" -uint8_t *mv_bar; -uint16_t mv_iobar; +static uint8_t *mv_bar; +static uint16_t mv_iobar; const struct dev_entry satas_mv[] = { /* 88SX6041 and 88SX6042 are the same according to the datasheet. */ -- To view, visit https://review.coreboot.org/c/flashrom/+/62612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.1.x Gerrit-Change-Id: I1e55138adef540e9d3a2237aa5b289cb338c0608 Gerrit-Change-Number: 62612 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in flashrom[1.1.x]: test_build.sh: Move build test procedure to repository
by Nico Huber (Code Review) 07 Mar '22

07 Mar '22

Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62617 ) Change subject: test_build.sh: Move build test procedure to repository ...................................................................... test_build.sh: Move build test procedure to repository Instead of hard coding the test procedure on qa.coreboot.org, allow running a script in the repo instead. The server is already adapted to do that, so once there's a test_build.sh file in the toplevel directory, it's run in place of the default operation. The content of this change mirrors the default operation exactly so should serve as a good starting point. The script is executed in an encapsulate[0] context with the workspace, /tmp and $HOME/.ccache writable, everything else read-only and network disabled. It should return 0 on success, anything else on failure, as is normal for UNIX processes. [0] https://review.coreboot.org/cgit/encapsulate.git (Backported minus the Meson support) Change-Id: I37a8e925d1b283c3b8f87cb3d0f1ed8920f2cf95 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46894 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62617 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: Nico Huber <nico.h(a)gmx.de> --- A test_build.sh 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Nico Huber: Verified Angel Pons: Looks good to me, approved Edward O'Callaghan: Looks good to me, but someone else must approve diff --git a/test_build.sh b/test_build.sh new file mode 100755 index 0000000..3ab5319 --- /dev/null +++ b/test_build.sh @@ -0,0 +1,4 @@ +#!/bin/sh +set -e + +make CONFIG_EVERYTHING=yes WARNERROR=yes -- To view, visit https://review.coreboot.org/c/flashrom/+/62617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.1.x Gerrit-Change-Id: I37a8e925d1b283c3b8f87cb3d0f1ed8920f2cf95 Gerrit-Change-Number: 62617 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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flashrom-gerrit March 2022