March 2022 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
by Nico Huber (Code Review) 09 Mar '22

09 Mar '22

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 ) Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq ...................................................................... Patch Set 17: (1 comment) Patchset: PS17: Edward, I think you just forked this project. Congrats. -- To view, visit https://review.coreboot.org/c/flashrom/+/61854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484 Gerrit-Change-Number: 61854 Gerrit-PatchSet: 17 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Alex Levin <levinale(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 09 Mar 2022 09:30:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: ite_ecfw: Implement support for flashing ITE ECs found on TUXEDO laptops
by Michael Niewöhner (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Felix Singer, Nico Huber, Michał Żygowski, Paul Menzel, Sergii Dmytruk. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55715 ) Change subject: ite_ecfw: Implement support for flashing ITE ECs found on TUXEDO laptops ...................................................................... Patch Set 29: (1 comment) File ite_ecfw.c: https://review.coreboot.org/c/flashrom/+/55715/comment/646bb8cc_d3429930 PS29, Line 411: } > that ite_ecfw_write() either always gets called for the whole flash at once Oh yes ofc, that's what I actually meant - `ite_ecfw_write`, not `ite_ecfw_write_block` -- To view, visit https://review.coreboot.org/c/flashrom/+/55715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I0e42260155ffea38a6f60790871cd8da7b657031 Gerrit-Change-Number: 55715 Gerrit-PatchSet: 29 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 09:27:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in flashrom[master]: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
by Edward O'Callaghan (Code Review) 09 Mar '22

09 Mar '22

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/61854 ) Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq ...................................................................... ichspi.c: Check SPI Cycle In-Progress prior start HW Seq As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. This bit remains set until the cycle completes on the SPI interface. Hardware automatically sets and clears this bit. Software must initiate the next SPI transaction when this bit is 0. Platform Setup: Alder Lake based ChromeOS devices (Brya variants) Replication Steps: Accepting and running firmware Auto Update (AU) on the Brya variants (dogfooder system) is seeing `flashrom` getting timed out. Problem Statement: Evidencing AU (Auto Update) failure while performing firmware update on the Alder Lake based ChromeOS devices. Observation: Based on the initial understanding from the failure log/pattern, it seems like the platform is evidencing multiple `flashrom` access from different source, for example: `futility` accesses flashrom for erase, write and read operation, `crossystem` uses flashrom for updating VBNV, additionally, `set_fw_good` script also uses `crossystem` to update the fw status. Solution: Without this SCIP check being implemented in flashrom, there is no way to ensure multiple instances of flashrom performing different SPI operations are not cancelling each other and running into below error: Erasing and writing flash chip... Timeout error between offset 0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED! Uh oh. Erase/write failed. Checking if anything has changed. TEST=Able to flash coreboot image on Alder Lake (Brya variants), Tiger Lake (Volteer variants), Kaby Lake (Eve system), Comet Lake (Hatch variants) and Ivybridge without any failure. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484 Reviewed-on: https://review.coreboot.org/c/flashrom/+/61854 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M ichspi.c 1 file changed, 17 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved diff --git a/ichspi.c b/ichspi.c index 84ac035..9f45ec2 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1402,6 +1402,11 @@ /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + if (REGREAD8(ICH9_REG_HSFS) & HSFS_SCIP) { + msg_perr("Error: SCIP bit is unexpectedly set.\n"); + return -1; + } + hsfc = REGREAD16(ICH9_REG_HSFC); hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ @@ -1439,6 +1444,12 @@ block_len = min(block_len, 256 - (addr & 0xFF)); ich_hwseq_set_addr(addr); + + if (REGREAD8(ICH9_REG_HSFS) & HSFS_SCIP) { + msg_perr("Error: SCIP bit is unexpectedly set.\n"); + return -1; + } + hsfc = REGREAD16(ICH9_REG_HSFC); hsfc &= ~hwseq_data.hsfc_fcycle; /* set read operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ @@ -1480,6 +1491,12 @@ /* as well as flash chip page borders as demanded in the Intel datasheets. */ block_len = min(block_len, 256 - (addr & 0xFF)); ich_fill_data(buf, block_len, ICH9_REG_FDATA0); + + if (REGREAD8(ICH9_REG_HSFS) & HSFS_SCIP) { + msg_perr("Error: SCIP bit is unexpectedly set.\n"); + return -1; + } + hsfc = REGREAD16(ICH9_REG_HSFC); hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */ hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ -- To view, visit https://review.coreboot.org/c/flashrom/+/61854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484 Gerrit-Change-Number: 61854 Gerrit-PatchSet: 17 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Alex Levin <levinale(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
by Edward O'Callaghan (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Patrick Georgi, Stefan Reinauer, Angel Pons, Sridhar Siricilla, Alex Levin, YH Lin, Nico Huber, Damien Zammit, Martin Roth, Subrata Banik, Caveh Jalali, David Hendricks, Tim Wawrzynczak, Nick Vaccaro, Boris Mittelberg. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 ) Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/61854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484 Gerrit-Change-Number: 61854 Gerrit-PatchSet: 16 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Alex Levin <levinale(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Alex Levin <levinale(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Damien Zammit Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 08:59:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: writeprotect.c: refactor and fix wp_mode functions
by Anastasia Klimchuk (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Nico Huber, Edward O'Callaghan, Angel Pons, Nikolai Artemiev. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62643 ) Change subject: writeprotect.c: refactor and fix wp_mode functions ...................................................................... Patch Set 2: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/62643/comment/dc75ddae_a400ebb4 PS2, Line 11: Given that is a follow up on previous patch, let's maybe add a reference. It would be easier to understand where this comes from. So you can say: This is a follow up on commit 12dbc4e04508aecfff53ad95b6f68865da1b4f07 Gerrit will add a link to a patch, which is very convenient. https://review.coreboot.org/c/flashrom/+/62643/comment/94248bf6_cf61eb49 PS2, Line 16: builds It might be fine, but just in case, maybe you have an environment with this patch already and you can run once? -- To view, visit https://review.coreboot.org/c/flashrom/+/62643 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib6c347453f9216e5816e4ed35bf9783fd3c720e0 Gerrit-Change-Number: 62643 Gerrit-PatchSet: 2 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 23:59:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: ite_ecfw: Implement support for flashing ITE ECs found on TUXEDO laptops
by Nico Huber (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Felix Singer, Michał Żygowski, Paul Menzel, Michael Niewöhner, Sergii Dmytruk. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55715 ) Change subject: ite_ecfw: Implement support for flashing ITE ECs found on TUXEDO laptops ...................................................................... Patch Set 29: (1 comment) File ite_ecfw.c: https://review.coreboot.org/c/flashrom/+/55715/comment/ef0ef4fb_ab153df3 PS29, Line 411: } > Ah, got it. […] Almost, I guess. We'd still need to split it into the real blocks. What the code already does. The existing code paths all seem fine, we'd just need to make sure that ite_ecfw_write() either always gets called for the whole flash at once or in the correct order. So that in this driver, we always take the same paths, i.e. write first block minus first 1KiB, write blocks... write last block, write first 1KiB. This needs to stay stable, AIUI. -- To view, visit https://review.coreboot.org/c/flashrom/+/55715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I0e42260155ffea38a6f60790871cd8da7b657031 Gerrit-Change-Number: 55715 Gerrit-PatchSet: 29 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 22:00:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in flashrom[master]: dmi: Correctly check for ERROR_PTR
by Nico Huber (Code Review) 08 Mar '22

08 Mar '22

Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62611 ) Change subject: dmi: Correctly check for ERROR_PTR ...................................................................... dmi: Correctly check for ERROR_PTR For the physmap*() functions, NULL is considered valid return value. Fixes a segmentation fault when DMI tables can't be mapped. Tested on intel/eblake board with broken coreboot. Change-Id: Ic403c2940c2b91acbd113f0acfa3ce9ef6c6bb6c Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62611 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M dmi.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/dmi.c b/dmi.c index 16d350d..a7b300d 100644 --- a/dmi.c +++ b/dmi.c @@ -164,7 +164,7 @@ unsigned int i = 0, j = 0; uint8_t *dmi_table_mem = physmap_ro("DMI Table", base, len); - if (dmi_table_mem == NULL) { + if (dmi_table_mem == ERROR_PTR) { msg_perr("Unable to access DMI Table\n"); return; } -- To view, visit https://review.coreboot.org/c/flashrom/+/62611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic403c2940c2b91acbd113f0acfa3ce9ef6c6bb6c Gerrit-Change-Number: 62611 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in flashrom[master]: flashchips.c: Mark MT25QU256 as tested
by Nico Huber (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Felix Singer, Angel Pons, Anastasia Klimchuk. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62664 ) Change subject: flashchips.c: Mark MT25QU256 as tested ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/62664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9d8b0038673185103ba08c9797ff94f2f7639d6c Gerrit-Change-Number: 62664 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Charles Parent <cha.parent(a)gmail.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 14:39:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: flashchips.c: Mark MT25QU256 as tested
by Angel Pons (Code Review) 08 Mar '22

08 Mar '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/62664 ) Change subject: flashchips.c: Mark MT25QU256 as tested ...................................................................... flashchips.c: Mark MT25QU256 as tested As reported by Charles Parent on the mailing list. Change-Id: I9d8b0038673185103ba08c9797ff94f2f7639d6c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M flashchips.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/62664/1 diff --git a/flashchips.c b/flashchips.c index acb7718..5cc5cdd 100644 --- a/flashchips.c +++ b/flashchips.c @@ -11771,7 +11771,7 @@ /* supports SFDP */ /* OTP: 64B total; read 0x4B, write 0x42 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = -- To view, visit https://review.coreboot.org/c/flashrom/+/62664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9d8b0038673185103ba08c9797ff94f2f7639d6c Gerrit-Change-Number: 62664 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
by Subrata Banik (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Patrick Georgi, Stefan Reinauer, Angel Pons, Sridhar Siricilla, Alex Levin, YH Lin, Nico Huber, Damien Zammit, Martin Roth, Caveh Jalali, David Hendricks, Tim Wawrzynczak, Nick Vaccaro, Boris Mittelberg. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 ) Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq ...................................................................... Patch Set 14: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/61854/comment/84f35221_3f4caee5 PS7, Line 25: TEST=Concurrent flashrom access is not throwing timeout. > I just tested this with Lenovo W530 (Ivybridge). I was able to read the bios region using a layout. > > ``` > * 1efdc43 (HEAD) ichspi.c: Check SPI Cycle In-Progress prior start HW Seq > | * 6289508 (origin/master, master) pcidev: Move scandev_inclass logic from internal to pcidev > | * bc2e3b6 ft2232_spi.c: Add FTDI FT4233H > | * 00194ea pcidev: Move pci_get_dev() logic into canonical place > | * 12dbc4e writeprotect: add {get,set}_wp_mode() > | * 4cb8464 writeprotect: add set_wp_range() > | * a548fe5 libflashrom,writeprotect: add flashrom_wp_get_available_ranges() > | * 2c3a2d6 writeprotect: add get_wp_range() for decoding ranges > | * 9fc100f flashchips,writeprotect_ranges: add range decoding function > | * cff87a8 libflashrom,writeprotect: add functions for reading/writing WP configs > | * 645e5e7 writeprotect.h: add structure to represent chip wp configuration bits > | * e007908 flash.h,flashchips.c: add writeprotect bit layout map to chips > |/ > * b7ea3a9 spi25_statusreg,flashchips: add SR2 read/write support > ``` > > [damien@zamlap flashrom]$ sudo ./flashrom -pinternal -V --noverify-all --layout ~/w530/layout --image bios -r ~/test.rom > flashrom v1.2-629-g1efdc43 on Linux 4.18.0-305.10.2.el8_4.x86_64 (x86_64) > flashrom is free software, get the source code at https://flashrom.org > > Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). > flashrom was built with unknown PCI library, GCC 8.4.1 20200928 (Red Hat 8.4.1-1), little endian > Command line (9 args): ./flashrom -pinternal -V --noverify-all --layout /home/damien/w530/layout --image bios -r /home/damien/test.rom > Added layout entry 00000000 - 00000fff named fd > Added layout entry 00500000 - 00bfffff named bios > Added layout entry 00003000 - 004fffff named me > Added layout entry 00001000 - 00002fff named gbe > Using region: "bios". > Initializing internal programmer > /sys/class/mtd/mtd0 does not exist > Found candidate at: 00000500-00000528 > Found coreboot table at 0x00000500. > Found candidate at: 00000000-00000c2c > Found coreboot table at 0x00000000. > coreboot table found at 0x7ff62000. > coreboot header(24) checksum: 19b0 table(3092) checksum: 486c entries: 34 > Vendor ID: LENOVO, part ID: ThinkPad W530 > Using Internal DMI decoder. > DMI string chassis-type: "Laptop" > Laptop detected via DMI. > DMI string system-manufacturer: "LENOVO" > DMI string system-product-name: "24384ZU" > DMI string system-version: "ThinkPad W530" > DMI string baseboard-manufacturer: "LENOVO" > DMI string baseboard-product-name: "24384ZU" > DMI string baseboard-version: "ThinkPad W530" > W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. > Active config mode, unknown reg 0x20 ID: 00. > Found chipset "Intel QM77" with PCI ID 8086:1e55. > Enabling flash write... Root Complex Register Block address = 0xfed1c000 > GCS = 0xc21: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) > Top Swap: not enabled > 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x4 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x5 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x6 > 0x7fffffff/0x7fffffff FWH IDSEL: 0x7 > 0x7fffffff/0x7fffffff FWH decode enabled > 0x7fffffff/0x7fffffff FWH decode enabled > 0x7fffffff/0x7fffffff FWH decode enabled > 0x7fffffff/0x7fffffff FWH decode enabled > 0x7fffffff/0x7fffffff FWH decode enabled > 0x7fffffff/0x7fffffff FWH decode enabled > 0x7fffffff/0x7fffffff FWH decode enabled > 0x7fffffff/0x7fffffff FWH decode enabled > 0x7fffffff/0x7fffffff FWH decode enabled > 0x7fffffff/0x7fffffff FWH decode enabled > 0x7fffffff/0x7fffffff FWH decode enabled > 0x7fffffff/0x7fffffff FWH decode enabled > Maximum FWH chip size: 0x100000 bytes > SPI Read Configuration: prefetching enabled, caching enabled, > BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled > SPIBAR = 0x00007f1ad053d000 + 0x3800 > 0x04: 0xe008 (HSFS) > HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 > SPI Configuration is locked down. > Reading OPCODES... done > 0x06: 0x3f00 (HSFC) > HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0 > 0x50: 0x00000a0b (FRAP) > BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b > 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only. > 0x58: 0x0bff0500 FREG1: BIOS region (0x00500000-0x00bfffff) is read-write. > 0x5C: 0x04ff0003 FREG2: Management Engine region (0x00003000-0x004fffff) is locked. > 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write. > Not all flash regions are freely accessible by flashrom. This is most likely > due to an active ME. Please see https://flashrom.org/ME for details. > At least some flash regions are read protected. You have to use a flash > layout and include only accessible regions. For write operations, you'll > additionally need the --noverify-all switch. See manpage for more details. > 0x90: 0xc0 (SSFS) > SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 > 0x91: 0xf90000 (SSFC) > SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=1 > 0x94: 0x5006 (PREOP) > 0x96: 0xb32d (OPTYPE) > 0x98: 0x05030201 (OPMENU) > 0x9c: 0x0bd89f20 (OPMENU+4) > 0xa0: 0x00000000 (BBAR) > 0xc4: 0x00802005 (LVSCC) > LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 > 0xc8: 0x00002005 (UVSCC) > UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 > 0xd0: 0x00000000 (FPB) > Enabling hardware sequencing due to multiple flash chips detected. > OK. > The following protocols are supported: Programmer-specific. > Probing for Programmer Opaque flash chip, 0 kB: Hardware sequencing reports 2 attached SPI flash chips with a combined density of 12288 kB. > Added layout entry 00000000 - 00bfffff named complete flash > Found Programmer flash chip "Opaque flash chip" (12288 kB, Programmer-specific) mapped at physical address 0x0000000000000000. > Found Programmer flash chip "Opaque flash chip" (12288 kB, Programmer-specific). > Reading flash... Reading 7340032 bytes starting at 0x500000. > done. > Restoring MMIO space at 0x7f1ad05408a0 > $ Thanks Damien for great help. -- To view, visit https://review.coreboot.org/c/flashrom/+/61854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484 Gerrit-Change-Number: 61854 Gerrit-PatchSet: 14 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Alex Levin <levinale(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Alex Levin <levinale(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Damien Zammit Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 03:56:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Damien Zammit Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: David Hendricks <david.hendricks(a)gmail.com> Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: comment

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flashrom-gerrit March 2022