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Change subject: util/lint: Introduce linter for git sign-off-by line
......................................................................
Patch Set 9: Code-Review+2
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Gerrit-Project: flashrom
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Gerrit-Change-Id: I03f1827803f8492d60a0a44174d5822c2265bfcb
Gerrit-Change-Number: 70079
Gerrit-PatchSet: 9
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
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Felix Singer has uploaded a new patch set (#2). ( https://review.coreboot.org/c/flashrom/+/70242 )
Change subject: test_build.sh: Switch to meson setup <dir>
......................................................................
test_build.sh: Switch to meson setup <dir>
Running the setup command as `meson [options]` instead of
`meson setup [options]` is ambiguous and deprecated.
Change-Id: I6e84997f910928d3973a4e5826a2d4196bdb2916
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M test_build.sh
1 file changed, 14 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/42/70242/2
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Gerrit-Change-Number: 70242
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Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/70218
to look at the new patch set (#2).
Change subject: flashrom.8.tmpl: Clarify supported ft2232_spi frequencies
......................................................................
flashrom.8.tmpl: Clarify supported ft2232_spi frequencies
The manpage suggests that ft2232_spi chips are only capable of up to
6 MHz SPI clock frequencies, whereas flashrom disables the divide-by-5
prescaler on the 'H' chips allowing up to 30 MHz frequencies. This
detail was already present in the comments of ft2232_spi.c.
Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com>
Change-Id: Id7690e1d4e11a3d0495afbc650f3c67430946468
---
M flashrom.8.tmpl
1 file changed, 17 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/70218/2
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70176 )
Change subject: README: Add information about meson and link build instructions
......................................................................
Patch Set 1: Code-Review+1
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Gerrit-Change-Number: 70176
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Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/70026 )
Change subject: internal.c: laptop_ok global state can become stale
......................................................................
internal.c: laptop_ok global state can become stale
Craask and similar DUT's are erroneously probing random second chips.
```
Found chipset "Intel Alder Lake-N".
Enabling flash write... SPI Configuration is locked down.
FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write.
FREG1: BIOS region (0x003a0000-0x00ffffff) is read-write.
FREG2: Management Engine region (0x00001000-0x0039ffff) is read-write.
OK.
Found Winbond flash chip "W25Q128.V..M" (16384 kB, Programmer-specific) on host.
Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed.
New value is 0x8b.
Found MoselVitelic flash chip "V29C51000T" (64 kB, Parallel) mapped at physical address 0x00000000ffff0000.
```
This seems to be due to `laptop_ok` becoming a stale global state
after the first operation leading to probing on unrelated buses.
Therefore unconditionally reset the global state upon entry into
the internal driver.
BUG=b:260518132,b:260151917
TEST=Craask reportly no longer finds duplicate chip.
Change-Id: I2c00c351904307eeb1488c5dfaffc91d6468ee25
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/70026
Reviewed-by: Sam McNally <sammc(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org>
---
M internal.c
1 file changed, 41 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Sam McNally: Looks good to me, approved
Anastasia Klimchuk: Looks good to me, approved
diff --git a/internal.c b/internal.c
index 4f68456..9b80f37 100644
--- a/internal.c
+++ b/internal.c
@@ -211,6 +211,9 @@
if (ret)
return ret;
+ /* Unconditionally reset global state from previous operation. */
+ laptop_ok = false;
+
/* Default to Parallel/LPC/FWH flash devices. If a known host controller
* is found, the host controller init routine sets the
* internal_buses_supported bitfield.
--
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70218 )
Change subject: flashrom.8.tmpl: Clarify supported ft2232_spi frequencies
......................................................................
Patch Set 1: Code-Review+2
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Gerrit-Change-Number: 70218
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Gerrit-Comment-Date: Thu, 01 Dec 2022 22:11:57 +0000
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Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/70218 )
Change subject: flashrom.8.tmpl: Clarify supported ft2232_spi frequencies
......................................................................
flashrom.8.tmpl: Clarify supported ft2232_spi frequencies
The manpage suggests that ft2232_spi chips are only capable of up to
12 MHz SPI clock frequencies, whereas flashrom disables the divide-by-5
prescaler on the 'H' chips allowing up to 60 MHz frequencies. This
detail was already present in the comments of ft2232_spi.c.
Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com>
Change-Id: Id7690e1d4e11a3d0495afbc650f3c67430946468
---
M flashrom.8.tmpl
1 file changed, 17 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/70218/1
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl
index e672869..26ddad0 100644
--- a/flashrom.8.tmpl
+++ b/flashrom.8.tmpl
@@ -939,8 +939,8 @@
expressible divisors are all
.B even
numbers between 2 and 2^17 (=131072) resulting in SPI clock frequencies of
-6 MHz down to about 92 Hz for 12 MHz inputs. The default divisor is set to 2, but you can use another one by
-specifying the optional
+6 MHz down to about 92 Hz for 12 MHz inputs (non-H chips) and 30 MHz down to about 458 Hz for 60 MHz inputs ('H' chips). The default
+divisor is set to 2, but you can use another one by specifying the optional
.B divisor
parameter with the
.sp
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70079 )
Change subject: util/lint: Introduce linter for git sign-off-by line
......................................................................
Patch Set 9:
(1 comment)
Patchset:
PS9:
Unfortunately the +2 got dropped :/
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Attention is currently required from: Edward O'Callaghan.
Hello build bot (Jenkins), Edward O'Callaghan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/70079
to look at the new patch set (#9).
Change subject: util/lint: Introduce linter for git sign-off-by line
......................................................................
util/lint: Introduce linter for git sign-off-by line
For compliance and to check if the commit message matches the
development guidelines, add a linter checking for the sign-off-by line
in the commit message. Also, hook it up to the test_build.sh script
which is used for CI builds.
These scripts were copied from the coreboot repository and were adjusted
so that they work for flashrom.
Change-Id: I03f1827803f8492d60a0a44174d5822c2265bfcb
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M test_build.sh
A util/lint/helper_functions.sh
A util/lint/lint-extended-020-signed-off-by
3 files changed, 93 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/70079/9
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