December 2022 - flashrom-gerrit

[M] Change in flashrom[master]: spi25.c: Move spi_get_opcode_from_erasefn() to spi.c
by Thomas Heijligen (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Simon Buhrow, Aarya. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67715 ) Change subject: spi25.c: Move spi_get_opcode_from_erasefn() to spi.c ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/67715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id654e998d0af2d3f5845336bb98b38d724519038 Gerrit-Change-Number: 67715 Gerrit-PatchSet: 5 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Simon Buhrow Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 18:30:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in flashrom[master]: spi.c: Add erasefn and opcodes for AT45 and S25F to lookup list
by Thomas Heijligen (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Simon Buhrow, Aarya. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67354 ) Change subject: spi.c: Add erasefn and opcodes for AT45 and S25F to lookup list ...................................................................... Patch Set 12: Code-Review-2 (1 comment) Patchset: PS12: This one should be abandoned. CB:67717 does the job -- To view, visit https://review.coreboot.org/c/flashrom/+/67354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ief25932120f940dea0ffe161a79219deecb2e8ab Gerrit-Change-Number: 67354 Gerrit-PatchSet: 12 Gerrit-Owner: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Simon Buhrow Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 18:23:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in flashrom[master]: spi.c: Move spi_get_erasefn_from_opcode to spi.c
by Thomas Heijligen (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Simon Buhrow, Nico Huber, Aarya. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67368 ) Change subject: spi.c: Move spi_get_erasefn_from_opcode to spi.c ...................................................................... Patch Set 9: Code-Review-2 (1 comment) Patchset: PS9: This one should be abandoned. CB:67715 does the job -- To view, visit https://review.coreboot.org/c/flashrom/+/67368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3263b7642c35e7fd1da0002175123e5560d94752 Gerrit-Change-Number: 67368 Gerrit-PatchSet: 9 Gerrit-Owner: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Simon Buhrow Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 18:22:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in flashrom[master]: README: Add information about meson and link build instructions
by Thomas Heijligen (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Felix Singer, Anastasia Klimchuk. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70176 ) Change subject: README: Add information about meson and link build instructions ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/flashrom/+/70176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2a27d8f2ba42e18be2485ae95bec1b4c874bb4f7 Gerrit-Change-Number: 70176 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Fri, 02 Dec 2022 12:58:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in flashrom[master]: meson.build: Rename conf object to config_manfile
by Thomas Heijligen (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Felix Singer. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70209 ) Change subject: meson.build: Rename conf object to config_manfile ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/70209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Icf24b9c47d4c7553f1ec045a9dfd3685b1376445 Gerrit-Change-Number: 70209 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Fri, 02 Dec 2022 12:57:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in flashrom[master]: tree/: Drop default_spi_probe_opcode for NULL case
by Felix Singer (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Thomas Heijligen, Edward O'Callaghan, Peter Marheine. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70264 ) Change subject: tree/: Drop default_spi_probe_opcode for NULL case ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/70264/comment/009cd79f_82dc57d3 PS1, Line 9: A NULL func pointer is necessary and sufficient for the Maybe give a bit more context about what the default function does. Suggestion: Instead of using a function that returns true for the default case, just use a null pointer since it's sufficient for that and thus this boilerplate is not needed. -- To view, visit https://review.coreboot.org/c/flashrom/+/70264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id502c5d2596ad1db52faf05723083620e4c52c12 Gerrit-Change-Number: 70264 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Fri, 02 Dec 2022 11:45:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in flashrom[master]: tree/: Drop default_spi_probe_opcode for NULL case
by Felix Singer (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Thomas Heijligen, Edward O'Callaghan, Peter Marheine. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70264 ) Change subject: tree/: Drop default_spi_probe_opcode for NULL case ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/70264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id502c5d2596ad1db52faf05723083620e4c52c12 Gerrit-Change-Number: 70264 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Fri, 02 Dec 2022 11:30:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in flashrom[master]: Makefile: Don't install git hooks automatically
by Felix Singer (Code Review) 02 Dec '22

02 Dec '22

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/68647 ) Change subject: Makefile: Don't install git hooks automatically ...................................................................... Patch Set 6: (1 comment) Patchset: PS4: > So, who does it? Done -- To view, visit https://review.coreboot.org/c/flashrom/+/68647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib83568c7ff149a8ec34ad7e92720c36a89def7bd Gerrit-Change-Number: 68647 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Dec 2022 11:28:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in flashrom[master]: cli_classic.c: Make count_max_decode_exceedings() pure
by Edward O'Callaghan (Code Review) 02 Dec '22

02 Dec '22

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/68479 ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: cli_classic.c: Make count_max_decode_exceedings() pure ...................................................................... cli_classic.c: Make count_max_decode_exceedings() pure Pass by argument the max_rom_decode structure such that the function is pure and defined upon its parameters. Note, unfortunately a itermediate step of a '_' suffix is required for the 'max_rom_decode' parameter as to not alias the global symbol within the function body. Change-Id: Ia01f77993deab68e251850008e885828e55b9462 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68479 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M cli_classic.c 1 file changed, 32 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/cli_classic.c b/cli_classic.c index fe50cf4..5cc14a0 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -520,43 +520,44 @@ /* Returns the number of buses commonly supported by the current programmer and flash chip where the latter * can not be completely accessed due to size/address limits of the programmer. */ -static unsigned int count_max_decode_exceedings(const struct flashctx *flash) +static unsigned int count_max_decode_exceedings(const struct flashctx *flash, + const struct decode_sizes *max_rom_decode_) { unsigned int limitexceeded = 0; uint32_t size = flash->chip->total_size * 1024; enum chipbustype buses = flash->mst->buses_supported & flash->chip->bustype; - if ((buses & BUS_PARALLEL) && (max_rom_decode.parallel < size)) { + if ((buses & BUS_PARALLEL) && (max_rom_decode_->parallel < size)) { limitexceeded++; msg_pdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, - max_rom_decode.parallel / 1024, "Parallel"); + max_rom_decode_->parallel / 1024, "Parallel"); } - if ((buses & BUS_LPC) && (max_rom_decode.lpc < size)) { + if ((buses & BUS_LPC) && (max_rom_decode_->lpc < size)) { limitexceeded++; msg_pdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, - max_rom_decode.lpc / 1024, "LPC"); + max_rom_decode_->lpc / 1024, "LPC"); } - if ((buses & BUS_FWH) && (max_rom_decode.fwh < size)) { + if ((buses & BUS_FWH) && (max_rom_decode_->fwh < size)) { limitexceeded++; msg_pdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, - max_rom_decode.fwh / 1024, "FWH"); + max_rom_decode_->fwh / 1024, "FWH"); } - if ((buses & BUS_SPI) && (max_rom_decode.spi < size)) { + if ((buses & BUS_SPI) && (max_rom_decode_->spi < size)) { limitexceeded++; msg_pdbg("Chip size %u kB is bigger than supported " "size %u kB of chipset/board/programmer " "for %s interface, " "probe/read/erase/write may fail. ", size / 1024, - max_rom_decode.spi / 1024, "SPI"); + max_rom_decode_->spi / 1024, "SPI"); } return limitexceeded; } @@ -1060,7 +1061,7 @@ print_chip_support_status(fill_flash->chip); - unsigned int limitexceeded = count_max_decode_exceedings(fill_flash); + unsigned int limitexceeded = count_max_decode_exceedings(fill_flash, &max_rom_decode); if (limitexceeded > 0 && !force) { enum chipbustype commonbuses = fill_flash->mst->buses_supported & fill_flash->chip->bustype; -- To view, visit https://review.coreboot.org/c/flashrom/+/68479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia01f77993deab68e251850008e885828e55b9462 Gerrit-Change-Number: 68479 Gerrit-PatchSet: 7 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in flashrom[master]: tree/: Drop default_spi_probe_opcode for NULL case
by Edward O'Callaghan (Code Review) 02 Dec '22

02 Dec '22

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/70264 ) Change subject: tree/: Drop default_spi_probe_opcode for NULL case ...................................................................... tree/: Drop default_spi_probe_opcode for NULL case A NULL func pointer is necessary and sufficient for the condition `NULL func pointer => true' as to not need this boilerplate. Ran; ``` $ find . -name '*.[c,h]' -exec sed -i '/.probe_opcode = default_spi_probe_opcode,/d' '{}' \; ``` Change-Id: Id502c5d2596ad1db52faf05723083620e4c52c12 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M bitbang_spi.c M buspirate_spi.c M ch341a_spi.c M dediprog.c M digilent_spi.c M dirtyjtag_spi.c M ft2232_spi.c M include/programmer.h M it87spi.c M jlink_spi.c M linux_spi.c M mediatek_i2c_spi.c M mstarddc_spi.c M ni845x_spi.c M parade_lspcon.c M pickit2_spi.c M raiden_debug_spi.c M realtek_mst_i2c_spi.c M sb600spi.c M serprog.c M spi.c M stlinkv3_spi.c M usbblaster_spi.c M wbsio_spi.c 24 files changed, 21 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/70264/1 diff --git a/bitbang_spi.c b/bitbang_spi.c index f7ded1f..67f6001 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -148,7 +148,6 @@ .write_256 = default_spi_write_256, .write_aai = default_spi_write_aai, .shutdown = bitbang_spi_shutdown, - .probe_opcode = default_spi_probe_opcode, }; int register_spi_bitbang_master(const struct bitbang_spi_master *master, void *spi_data) diff --git a/buspirate_spi.c b/buspirate_spi.c index dbaac4e..410f6f7 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -183,7 +183,6 @@ .write_256 = default_spi_write_256, .write_aai = default_spi_write_aai, .shutdown = buspirate_spi_shutdown, - .probe_opcode = default_spi_probe_opcode, }; static const struct buspirate_speeds spispeeds[] = { diff --git a/ch341a_spi.c b/ch341a_spi.c index 294a6a6..7400b40 100644 --- a/ch341a_spi.c +++ b/ch341a_spi.c @@ -418,7 +418,6 @@ .write_256 = default_spi_write_256, .write_aai = default_spi_write_aai, .shutdown = ch341a_spi_shutdown, - .probe_opcode = default_spi_probe_opcode, }; static int ch341a_spi_init(const struct programmer_cfg *cfg) diff --git a/dediprog.c b/dediprog.c index b4279d8..478a33d 100644 --- a/dediprog.c +++ b/dediprog.c @@ -1039,7 +1039,6 @@ .write_256 = dediprog_spi_write_256, .write_aai = dediprog_spi_write_aai, .shutdown = dediprog_shutdown, - .probe_opcode = default_spi_probe_opcode, }; /* diff --git a/digilent_spi.c b/digilent_spi.c index 6575cbf..70bf58d 100644 --- a/digilent_spi.c +++ b/digilent_spi.c @@ -338,7 +338,6 @@ .write_256 = default_spi_write_256, .write_aai = default_spi_write_aai, .shutdown = digilent_spi_shutdown, - .probe_opcode = default_spi_probe_opcode, }; static bool default_reset(struct libusb_device_handle *handle) diff --git a/dirtyjtag_spi.c b/dirtyjtag_spi.c index 42169ed..42445ad 100644 --- a/dirtyjtag_spi.c +++ b/dirtyjtag_spi.c @@ -198,7 +198,6 @@ .write_256 = default_spi_write_256, .write_aai = default_spi_write_aai, .shutdown = dirtyjtag_spi_shutdown, - .probe_opcode = default_spi_probe_opcode, }; static int dirtyjtag_spi_init(const struct programmer_cfg *cfg) diff --git a/ft2232_spi.c b/ft2232_spi.c index aec21bc..ff88d20 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -301,7 +301,6 @@ .write_256 = default_spi_write_256, .write_aai = default_spi_write_aai, .shutdown = ft2232_shutdown, - .probe_opcode = default_spi_probe_opcode, }; /* Returns 0 upon success, a negative number upon errors. */ diff --git a/include/programmer.h b/include/programmer.h index 55e300a..bbe397d 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -312,7 +312,7 @@ int (*write_256)(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int (*write_aai)(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int (*shutdown)(void *data); - bool (*probe_opcode)(struct flashctx *flash, uint8_t opcode); + bool (*probe_opcode)(struct flashctx *flash, uint8_t opcode); /* NULL func implies true. */ void *data; }; @@ -322,7 +322,6 @@ int default_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int default_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int default_spi_write_aai(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); -bool default_spi_probe_opcode(struct flashctx *flash, uint8_t opcode); int register_spi_master(const struct spi_master *mst, void *data); /* The following enum is needed by ich_descriptor_tool and ich* code as well as in chipset_enable.c. */ diff --git a/it87spi.c b/it87spi.c index a022041..7893900 100644 --- a/it87spi.c +++ b/it87spi.c @@ -321,7 +321,6 @@ .write_256 = it8716f_spi_chip_write_256, .write_aai = spi_chip_write_1, .shutdown = it8716f_shutdown, - .probe_opcode = default_spi_probe_opcode, }; static uint16_t it87spi_probe(const struct programmer_cfg *cfg, uint16_t port) diff --git a/jlink_spi.c b/jlink_spi.c index 63d15b8..49c6216 100644 --- a/jlink_spi.c +++ b/jlink_spi.c @@ -190,7 +190,6 @@ .write_aai = default_spi_write_aai, .features = SPI_MASTER_4BA, .shutdown = jlink_spi_shutdown, - .probe_opcode = default_spi_probe_opcode, }; static int jlink_spi_init(const struct programmer_cfg *cfg) diff --git a/linux_spi.c b/linux_spi.c index ee02304..e599e94 100644 --- a/linux_spi.c +++ b/linux_spi.c @@ -121,7 +121,6 @@ .write_256 = linux_spi_write_256, .write_aai = default_spi_write_aai, .shutdown = linux_spi_shutdown, - .probe_opcode = default_spi_probe_opcode, }; /* Read max buffer size from sysfs, or use page size as fallback. */ diff --git a/mediatek_i2c_spi.c b/mediatek_i2c_spi.c index 3aa9dd9..2fc1cd9 100644 --- a/mediatek_i2c_spi.c +++ b/mediatek_i2c_spi.c @@ -461,7 +461,6 @@ .write_256 = default_spi_write_256, .write_aai = default_spi_write_aai, .shutdown = mediatek_shutdown, - .probe_opcode = default_spi_probe_opcode, }; static int get_params(const struct programmer_cfg *cfg, bool *allow_brick) diff --git a/mstarddc_spi.c b/mstarddc_spi.c index 0c11717..09d54a0 100644 --- a/mstarddc_spi.c +++ b/mstarddc_spi.c @@ -147,7 +147,6 @@ .write_256 = default_spi_write_256, .write_aai = default_spi_write_aai, .shutdown = mstarddc_spi_shutdown, - .probe_opcode = default_spi_probe_opcode, }; /* Returns 0 upon success, a negative number upon errors. */ diff --git a/ni845x_spi.c b/ni845x_spi.c index 2750334..f418ab9 100644 --- a/ni845x_spi.c +++ b/ni845x_spi.c @@ -537,7 +537,6 @@ .write_256 = default_spi_write_256, .write_aai = default_spi_write_aai, .shutdown = ni845x_spi_shutdown, - .probe_opcode = default_spi_probe_opcode, }; static int ni845x_spi_init(const struct programmer_cfg *cfg) diff --git a/parade_lspcon.c b/parade_lspcon.c index a50346e..88ac5bd 100644 --- a/parade_lspcon.c +++ b/parade_lspcon.c @@ -437,7 +437,6 @@ .write_256 = parade_lspcon_write_256, .write_aai = parade_lspcon_write_aai, .shutdown = parade_lspcon_shutdown, - .probe_opcode = default_spi_probe_opcode, }; static int get_params(const struct programmer_cfg *cfg, bool *allow_brick) diff --git a/pickit2_spi.c b/pickit2_spi.c index e8c80af..a2518d2 100644 --- a/pickit2_spi.c +++ b/pickit2_spi.c @@ -385,7 +385,6 @@ .write_256 = default_spi_write_256, .write_aai = default_spi_write_aai, .shutdown = pickit2_shutdown, - .probe_opcode = default_spi_probe_opcode, }; static int pickit2_spi_init(const struct programmer_cfg *cfg) diff --git a/raiden_debug_spi.c b/raiden_debug_spi.c index 517b173..bb72081 100644 --- a/raiden_debug_spi.c +++ b/raiden_debug_spi.c @@ -1325,7 +1325,6 @@ .write_256 = default_spi_write_256, .write_aai = default_spi_write_aai, .shutdown = raiden_debug_spi_shutdown, - .probe_opcode = default_spi_probe_opcode, }; static int match_endpoint(struct libusb_endpoint_descriptor const *descriptor, diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 2a5d5ed..1e9d8a3 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -441,7 +441,6 @@ .write_256 = realtek_mst_i2c_spi_write_256, .write_aai = realtek_mst_i2c_spi_write_aai, .shutdown = realtek_mst_i2c_spi_shutdown, - .probe_opcode = default_spi_probe_opcode, }; static int get_params(const struct programmer_cfg *cfg, bool *reset, bool *enter_isp, bool *allow_brick) diff --git a/sb600spi.c b/sb600spi.c index 8c018a3..40b7778 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -606,7 +606,6 @@ .write_256 = default_spi_write_256, .write_aai = default_spi_write_aai, .shutdown = sb600spi_shutdown, - .probe_opcode = default_spi_probe_opcode, }; static const struct spi_master spi_master_yangtze = { @@ -620,7 +619,6 @@ .write_256 = default_spi_write_256, .write_aai = default_spi_write_aai, .shutdown = sb600spi_shutdown, - .probe_opcode = default_spi_probe_opcode, }; static const struct spi_master spi_master_promontory = { @@ -634,7 +632,6 @@ .write_256 = default_spi_write_256, .write_aai = default_spi_write_aai, .shutdown = sb600spi_shutdown, - .probe_opcode = default_spi_probe_opcode, }; int sb600_probe_spi(const struct programmer_cfg *cfg, struct pci_dev *dev) diff --git a/serprog.c b/serprog.c index a3a3db3..fbf4cf6 100644 --- a/serprog.c +++ b/serprog.c @@ -463,7 +463,6 @@ .read = default_spi_read, .write_256 = default_spi_write_256, .write_aai = default_spi_write_aai, - .probe_opcode = default_spi_probe_opcode, }; static int sp_check_opbuf_usage(int bytes_to_be_added) diff --git a/spi.c b/spi.c index 38d8d01..9f820d7 100644 --- a/spi.c +++ b/spi.c @@ -134,11 +134,6 @@ return flash->mst->spi.write_aai(flash, buf, start, len); } -bool default_spi_probe_opcode(struct flashctx *flash, uint8_t opcode) -{ - return true; -} - int register_spi_master(const struct spi_master *mst, void *data) { struct registered_master rmst = {0}; @@ -151,7 +146,7 @@ } if (!mst->write_aai || !mst->write_256 || !mst->read || !mst->command || - !mst->multicommand || !mst->probe_opcode || + !mst->multicommand || ((mst->command == default_spi_send_command) && (mst->multicommand == default_spi_send_multicommand))) { msg_perr("%s called with incomplete master definition. " diff --git a/stlinkv3_spi.c b/stlinkv3_spi.c index 1d5763b..3b2837b 100644 --- a/stlinkv3_spi.c +++ b/stlinkv3_spi.c @@ -471,7 +471,6 @@ .write_256 = default_spi_write_256, .write_aai = default_spi_write_aai, .shutdown = stlinkv3_spi_shutdown, - .probe_opcode = default_spi_probe_opcode, }; static int stlinkv3_spi_init(const struct programmer_cfg *cfg) diff --git a/usbblaster_spi.c b/usbblaster_spi.c index 5e2c020..8c52ec6 100644 --- a/usbblaster_spi.c +++ b/usbblaster_spi.c @@ -173,7 +173,6 @@ .write_256 = default_spi_write_256, .write_aai = default_spi_write_aai, .shutdown = usbblaster_shutdown, - .probe_opcode = default_spi_probe_opcode, }; /* Returns 0 upon success, a negative number upon errors. */ diff --git a/wbsio_spi.c b/wbsio_spi.c index 1aa8729..04bb08f 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -193,7 +193,6 @@ .write_256 = spi_chip_write_1, .write_aai = spi_chip_write_1, .shutdown = wbsio_spi_shutdown, - .probe_opcode = default_spi_probe_opcode, }; int wbsio_check_for_spi(void) -- To view, visit https://review.coreboot.org/c/flashrom/+/70264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id502c5d2596ad1db52faf05723083620e4c52c12 Gerrit-Change-Number: 70264 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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flashrom-gerrit December 2022