December 2022 - flashrom-gerrit

[S] Change in flashrom[1.3.x]: libpayload: Fix compiling bugs
by Felix Singer (Code Review) 01 Dec '22

01 Dec '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/flashrom/+/70040 ) Change subject: libpayload: Fix compiling bugs ...................................................................... libpayload: Fix compiling bugs hwaccess_physmap.c: make `void *sys_physmap()` static hwaccess_x86_io.c: Add missing include Original-Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69831 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Original-Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Original-Reviewed-by: Nico Huber <nico.h(a)gmx.de> Original-Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I5062c5a62b90f7a189488f3f569dc357bd2cb85f Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70040 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M hwaccess_physmap.c M hwaccess_x86_io.c 2 files changed, 28 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/hwaccess_physmap.c b/hwaccess_physmap.c index 81adf18..f95b5f6 100644 --- a/hwaccess_physmap.c +++ b/hwaccess_physmap.c @@ -121,7 +121,7 @@ #define MEM_DEV "" -void *sys_physmap(uintptr_t phys_addr, size_t len) +static void *sys_physmap(uintptr_t phys_addr, size_t len) { return (void *)phys_to_virt(phys_addr); } diff --git a/hwaccess_x86_io.c b/hwaccess_x86_io.c index c3ad313..a883ed4 100644 --- a/hwaccess_x86_io.c +++ b/hwaccess_x86_io.c @@ -134,6 +134,8 @@ #endif #if defined(__LIBPAYLOAD__) +#include <arch/io.h> + #define IO_PORT_PERMISSION USE_DUMMY #define IO_PORT_FUNCTION USE_LIBC_TARGET_LAST #endif -- To view, visit https://review.coreboot.org/c/flashrom/+/70040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: I5062c5a62b90f7a189488f3f569dc357bd2cb85f Gerrit-Change-Number: 70040 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: merged

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[S] Change in flashrom[1.3.x]: libpayload: Fix compiling bugs
by Anastasia Klimchuk (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Felix Singer, Angel Pons. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70040 ) Change subject: libpayload: Fix compiling bugs ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/70040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: I5062c5a62b90f7a189488f3f569dc357bd2cb85f Gerrit-Change-Number: 70040 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Dec 2022 11:44:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in flashrom[1.3.x]: ichspi: Fix number of bytes for HW seq operations
by Felix Singer (Code Review) 01 Dec '22

01 Dec '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/flashrom/+/70039 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: ichspi: Fix number of bytes for HW seq operations ...................................................................... ichspi: Fix number of bytes for HW seq operations This patch fixes a potential issue where the SPI controller register HSFC.FDBC (bits 24-29) value gets incorrectly calculated while passing the `len` as `0` instead of `1`. As per Intel EDS, `0b` in the FDBC represents 1 byte while `0x3f` represents 64-bytes to be transferred. The number of bytes transferred is the value of this field plus 1. If we would like to transfer 1 byte then we need to set `0b` in FDBC for operations like read, write, flash id as to account for the `set byte count` hence, the `len` argument should be `1`. Additionally, as per EDS, the FDBC field is ignored for any block erase command. BUG=b:258280679 TEST=Able to build flashrom and perform below operations on Google, Rex and Google, Kano/Taeko. During `--wp-disable` HW seq operation that requires 1 byte data transfer. HSFC.FDBC value while passing `len` as `0` = 0x3f (represents 64-byte) HSFC.FDBC value while passing `len` as `1` = 0x0 (represents 1-byte) Original-Signed-off-by: Subrata Banik <subratabanik(a)google.com> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69789 Original-Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Original-Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Original-Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com> Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Change-Id: I5b911655649c693e576497520687d7810bbd3c54 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70039 Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M ichspi.c 1 file changed, 56 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved Anastasia Klimchuk: Looks good to me, but someone else must approve diff --git a/ichspi.c b/ichspi.c index 29dcd25..dd5a2c1 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1360,6 +1360,12 @@ /* Set up transaction parameters. */ hsfc |= hsfc_cycle; + /* + * The number of bytes transferred is the value of `FDBC` plus 1, hence, + * subtracted 1 from the length field. + * As per Intel EDS, `0b` in the FDBC represents 1 byte while `0x3f` + * represents 64-bytes to be transferred. + */ hsfc |= HSFC_FDBC_VAL(len - 1); hsfc |= HSFC_FGO; /* start */ prettyprint_ich9_reg_hsfc(hsfc, ich_generation); @@ -1399,7 +1405,7 @@ } msg_pdbg("Reading Status register\n"); - if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_RD_STATUS, 0, len, ich_generation, + if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_RD_STATUS, 1, len, ich_generation, hwseq_data->addr_mask)) { msg_perr("Reading Status register failed\n!!"); return -1; @@ -1422,7 +1428,7 @@ ich_fill_data(&value, len, ICH9_REG_FDATA0); - if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_WR_STATUS, 0, len, ich_generation, + if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_WR_STATUS, 1, len, ich_generation, hwseq_data->addr_mask)) { msg_perr("Writing Status register failed\n!!"); return -1; @@ -1518,7 +1524,7 @@ msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); - if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_BLOCK_ERASE, addr, 0, ich_generation, + if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_BLOCK_ERASE, addr, 1, ich_generation, hwseq_data->addr_mask)) return -1; return 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/70039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: I5b911655649c693e576497520687d7810bbd3c54 Gerrit-Change-Number: 70039 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: merged

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[M] Change in flashrom[1.3.x]: ichspi: Clear Fast SPI HSFC register before HW seq operation
by Felix Singer (Code Review) 01 Dec '22

01 Dec '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/flashrom/+/69998 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: ichspi: Clear Fast SPI HSFC register before HW seq operation ...................................................................... ichspi: Clear Fast SPI HSFC register before HW seq operation This patch fixes a regression introduced with commit 7ed1337309d3fe74f5af09520970f0f1d417399a (ichspi: Factor out common hwseq_xfer logic into helpers). The reason for the regression is ignoring the fact that the Fast SPI controller MMIO register HSFC (0x06) might not hold the default zero value before initiating the HW sequencing operation. Having a `1b` value in the HSFC.FDBC (bits 24-29) field would represent a byte that needs to be transfered. While debugging the regression, we have observed that the default value in the FDBC (prior to initiate any operation) is 0x3f (instead of zero) which represents 64-byte transfer. localhost ~ # iotools mmio_read32 0x92d16006 0x3f00 <Fast SPI MMIO BAR: 0x92d16000 and HSFC offset: 0x06> FDBC offset during `--wp-disable` operation represents higher numbers of bytes than the actual and eventually results in the error. Additionally, dropped unused variable (struct hwseq_data *hwseq_data). BUG=b:258280679 TEST=Able to build flashrom and perform below operations on Google, Rex and Google, Kano/Taeko. Without this patch: HSFC register value inside ich_start_hwseq_xfer() before initiating the HW seq operations: 0x3f00 HSFC register value inside ich_start_hwseq_xfer() during the HW seq operations (Read Status): 0x3f11 With this patch: HSFC register value inside ich_start_hwseq_xfer() before initiating the HW seq operations: 0x0 HSFC register value inside ich_start_hwseq_xfer() during the HW seq operations (Read Status): 0x11 Additionally, verified other HW sequencing operations (like read, write, erase, read status, write status, read ID) working fine without any error. Original-Signed-off-by: Subrata Banik <subratabanik(a)google.com> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69788 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Original-Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com> Change-Id: I4cc3f24f880d1d621f1f48a6e6b276449fa46f98 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69998 Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M ichspi.c 1 file changed, 69 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved Anastasia Klimchuk: Looks good to me, but someone else must approve diff --git a/ichspi.c b/ichspi.c index cd6e802..29dcd25 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1349,8 +1349,8 @@ uint32_t hsfc_cycle, uint32_t flash_addr, size_t len, uint32_t addr_mask) { - uint16_t hsfc; - struct hwseq_data *hwseq_data = get_hwseq_data_from_context(flash); + /* make sure HSFC register is cleared before initiate any operation */ + uint16_t hsfc = 0; /* Sets flash_addr in FADDR */ ich_hwseq_set_addr(flash_addr, addr_mask); @@ -1359,8 +1359,6 @@ REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); /* Set up transaction parameters. */ - hsfc = REGREAD16(ICH9_REG_HSFC); - hsfc &= ~hwseq_data->hsfc_fcycle; /* clear operation */ hsfc |= hsfc_cycle; hsfc |= HSFC_FDBC_VAL(len - 1); hsfc |= HSFC_FGO; /* start */ -- To view, visit https://review.coreboot.org/c/flashrom/+/69998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: I4cc3f24f880d1d621f1f48a6e6b276449fa46f98 Gerrit-Change-Number: 69998 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: merged

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[S] Change in flashrom[1.3.x]: flashchips.c: Add 4BA write to XM25Qx256C
by Felix Singer (Code Review) 01 Dec '22

01 Dec '22

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/70204 ) Change subject: flashchips.c: Add 4BA write to XM25Qx256C ...................................................................... flashchips.c: Add 4BA write to XM25Qx256C Flash chips XM25QH256C and XM25QU256C support the 4-byte program command (0x12) according to their datasheets, but the feature flag is not enabled in flashchips.c, so enable it to allow this feature to be used. TICKET: https://ticket.coreboot.org/issues/371 BUG=b:259493706 TEST=build Original-Signed-off-by: Liam Flaherty <liamflaherty(a)chromium.org> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69713 Original-Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Change-Id: I96c80762fcda2af6028c7a53d8c545b0c6565cbd Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M flashchips.c 1 file changed, 29 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/04/70204/1 diff --git a/flashchips.c b/flashchips.c index 6fc3a84..76f3fbb 100644 --- a/flashchips.c +++ b/flashchips.c @@ -19807,7 +19807,7 @@ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ | - FEATURE_WRSR2, + FEATURE_4BA_WRITE | FEATURE_WRSR2, .tested = TEST_UNTESTED, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, @@ -19856,7 +19856,8 @@ /* supports SFDP */ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN - | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ, + | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ + | FEATURE_4BA_WRITE, .tested = TEST_UNTESTED, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, -- To view, visit https://review.coreboot.org/c/flashrom/+/70204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: I96c80762fcda2af6028c7a53d8c545b0c6565cbd Gerrit-Change-Number: 70204 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Liam Flaherty <liamflaherty(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in flashrom[1.3.x]: opaque_master: Mark Opaque chip as tested for WP
by Felix Singer (Code Review) 01 Dec '22

01 Dec '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/flashrom/+/69997 ) Change subject: opaque_master: Mark Opaque chip as tested for WP ...................................................................... opaque_master: Mark Opaque chip as tested for WP Opaque masters, by design, populate the flashchip structure during the execution of their probe function. Therefore any opaque master operation displays a message to the user: "This flash part has status UNTESTED for operations: WP". However, for all the other operations (read, write, erase) opaque masters always mark them as tested. Thus, align WP as marked tested inline with other opaque chip operations. BUG=b:258755442 TEST=the following does not display untested message: 1) flashrom -p dummy:size=8388608,emulate=VARIABLE_SIZE 2) flashrom -p internal (on Intel device) Original-Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69842 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Original-Reviewed-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Original-Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I5ae4cb49eb0abc6ab26cfe2f3359e4e50dd4fd4f Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69997 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M dummyflasher.c M ichspi.c M nicintel_eeprom.c 3 files changed, 38 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/dummyflasher.c b/dummyflasher.c index 110a88c..35cdfef 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -145,7 +145,7 @@ msg_cdbg("%s: set flash->total_size to %dK bytes.\n", __func__, flash->chip->total_size); - flash->chip->tested = TEST_OK_PREW; + flash->chip->tested = TEST_OK_PREWB; if (emu_data->erase_to_zero) flash->chip->feature_bits |= FEATURE_ERASED_ZERO; diff --git a/ichspi.c b/ichspi.c index b3beaea..cd6e802 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1485,7 +1485,7 @@ msg_cdbg("In that range are %d erase blocks with %d B each.\n", size_high / erase_size_high, erase_size_high); } - flash->chip->tested = TEST_OK_PREW; + flash->chip->tested = TEST_OK_PREWB; return 1; } diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index ff2c3ce..4d5ab6b 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -115,7 +115,7 @@ /* Emulated eeprom has a fixed size of 4 KB */ flash->chip->total_size = 4; flash->chip->page_size = flash->chip->total_size * 1024; - flash->chip->tested = TEST_OK_PREW; + flash->chip->tested = TEST_OK_PREWB; flash->chip->gran = write_gran_1byte_implicit_erase; flash->chip->block_erasers->eraseblocks[0].size = flash->chip->page_size; flash->chip->block_erasers->eraseblocks[0].count = 1; @@ -146,7 +146,7 @@ } flash->chip->page_size = EE_PAGE_MASK + 1; - flash->chip->tested = TEST_OK_PREW; + flash->chip->tested = TEST_OK_PREWB; flash->chip->gran = write_gran_1byte_implicit_erase; flash->chip->block_erasers->eraseblocks[0].size = (EE_PAGE_MASK + 1); flash->chip->block_erasers->eraseblocks[0].count = (flash->chip->total_size * 1024) / (EE_PAGE_MASK + 1); -- To view, visit https://review.coreboot.org/c/flashrom/+/69997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: I5ae4cb49eb0abc6ab26cfe2f3359e4e50dd4fd4f Gerrit-Change-Number: 69997 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in flashrom[1.3.x]: linux_mtd: Mark Opaque chip as tested for WP
by Felix Singer (Code Review) 01 Dec '22

01 Dec '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/flashrom/+/69996 ) Change subject: linux_mtd: Mark Opaque chip as tested for WP ...................................................................... linux_mtd: Mark Opaque chip as tested for WP Since linux_mtd supports write-protect, its probe function needs to mark Opaque chip as tested for WP. Programmers which are opaque masters are responsible for populating flashchip#tested struct in probe function. Without the patch, any operation running via linux_mtd displays a message "This flash part has status UNTESTED for operations: WP". With the patch, the message is not displayed anymore. BUG=b:258755442 BRANCH=none TEST=flashrom -p host on ARM dut Found Programmer flash chip "Opaque flash chip" (8192 kB, Programmer-specific) on host. No operations were specified. Original-Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69518 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Original-Reviewed-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Change-Id: Icc0521c28555a93f26ce66bdbeaa68590f10c358 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69996 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M linux_mtd.c 1 file changed, 36 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/linux_mtd.c b/linux_mtd.c index 5a1360e..c49b14a 100644 --- a/linux_mtd.c +++ b/linux_mtd.c @@ -179,7 +179,7 @@ if (data->no_erase) flash->chip->feature_bits |= FEATURE_NO_ERASE; - flash->chip->tested = TEST_OK_PREW; + flash->chip->tested = TEST_OK_PREWB; flash->chip->total_size = data->total_size / 1024; /* bytes -> kB */ flash->chip->block_erasers[0].eraseblocks[0].size = data->erasesize; flash->chip->block_erasers[0].eraseblocks[0].count = -- To view, visit https://review.coreboot.org/c/flashrom/+/69996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: Icc0521c28555a93f26ce66bdbeaa68590f10c358 Gerrit-Change-Number: 69996 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in flashrom[1.3.x]: cli_classic.c: Be consistent with pointer types
by Felix Singer (Code Review) 01 Dec '22

01 Dec '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/flashrom/+/69995 ) Change subject: cli_classic.c: Be consistent with pointer types ...................................................................... cli_classic.c: Be consistent with pointer types With `i586-pc-msdosdjgpp-gcc (GCC) 12.2.0`, `uint32_t` is defined as `long unsigned int`, which is not the same as `unsigned int`. As the `flashrom_layout_get_region_range()` function is part of libflashrom API, adjust `cli_classic.c` instead to avoid type mismatches. Original-Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69451 Original-Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Original-Reviewed-by: Evan Benn <evanbenn(a)google.com> Original-Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com> Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Change-Id: Ie8f5bc0d9296f7c6b8f8a351b53052f5fe86b09d Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69995 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M cli_classic.c 1 file changed, 28 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved Anastasia Klimchuk: Looks good to me, but someone else must approve diff --git a/cli_classic.c b/cli_classic.c index a77422e..4649c73 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -126,7 +126,7 @@ return true; } -static int parse_wp_range(uint32_t *start, uint32_t *len) +static int parse_wp_range(unsigned int *start, unsigned int *len) { char *endptr = NULL, *token = NULL; @@ -568,7 +568,7 @@ int namelen, opt, i, j; int startchip = -1, chipcount = 0, option_index = 0; int operation_specified = 0; - uint32_t wp_start = 0, wp_len = 0; + unsigned int wp_start = 0, wp_len = 0; bool force = false, ifd = false, fmap = false; #if CONFIG_PRINT_WIKI == 1 bool list_supported_wiki = false; -- To view, visit https://review.coreboot.org/c/flashrom/+/69995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: Ie8f5bc0d9296f7c6b8f8a351b53052f5fe86b09d Gerrit-Change-Number: 69995 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: merged

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[M] Change in flashrom[master]: ichspi: Handle EC region permissions
by Nikolai Artemiev (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Nikolai Artemiev. Hello build bot (Jenkins), Edward O'Callaghan, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/70169 to look at the new patch set (#4). Change subject: ichspi: Handle EC region permissions ...................................................................... ichspi: Handle EC region permissions WIP. Not sure if we need this. BUG=b:260440773 BRANCH=none TEST=todo Change-Id: Ieaf2a960ec0c72d7b576dc3733260592c7c1f766 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M ichspi.c 1 file changed, 53 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/69/70169/4 -- To view, visit https://review.coreboot.org/c/flashrom/+/70169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ieaf2a960ec0c72d7b576dc3733260592c7c1f766 Gerrit-Change-Number: 70169 Gerrit-PatchSet: 4 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in flashrom[master]: flashrom: Skip read/write/erase/verify ops on inaccessable flash regions
by Nikolai Artemiev (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Nikolai Artemiev. Hello build bot (Jenkins), Edward O'Callaghan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/70128 to look at the new patch set (#7). Change subject: flashrom: Skip read/write/erase/verify ops on inaccessable flash regions ...................................................................... flashrom: Skip read/write/erase/verify ops on inaccessable flash regions Skip flash regions that get_region() indicates are inaccessable. This fixes transaction errors due to accessing invalid flash regions on Intel platforms with active an CSME coprocessor. BUG=b:260440773 BRANCH=none TEST=flashrom -{r,w,E,v} on dedede (JSL) Change-Id: I9b96fb04b863625d2c9f9a00b97c35b3ddb0871b Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M flashrom.c 1 file changed, 179 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/28/70128/7 -- To view, visit https://review.coreboot.org/c/flashrom/+/70128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9b96fb04b863625d2c9f9a00b97c35b3ddb0871b Gerrit-Change-Number: 70128 Gerrit-PatchSet: 7 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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