Gabriel Tremblay has abandoned this change. ( https://review.coreboot.org/c/flashrom/+/70211 )
Change subject: Added support for Macronix MX25V1635F Tested working on a new chip with raspberrypi spi.
......................................................................
Abandoned
Some side modifications polluted the commit.
--
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I86088b663d6eb26895956c4c8b4ca5a79c619535
Gerrit-Change-Number: 70211
Gerrit-PatchSet: 1
Gerrit-Owner: Gabriel Tremblay
Gerrit-MessageType: abandon
Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/70209 )
Change subject: meson.build: Rename conf object to config_manfile
......................................................................
meson.build: Rename conf object to config_manfile
The config data in the conf object is specific to the man file. Thus,
rename it accordingly and also move the declaration to the place where
it is used.
Change-Id: Icf24b9c47d4c7553f1ec045a9dfd3685b1376445
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M meson.build
1 file changed, 18 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/09/70209/1
diff --git a/meson.build b/meson.build
index 14a84ac..859256f 100644
--- a/meson.build
+++ b/meson.build
@@ -28,8 +28,6 @@
'-Wno-missing-braces',
]
-conf = configuration_data()
-
cc = meson.get_compiler('c')
add_project_arguments(cc.get_supported_arguments(warning_flags), language : 'c')
add_project_arguments('-D_DEFAULT_SOURCE', language : 'c')
@@ -591,12 +589,13 @@
description : 'library to interact with flashrom',
)
-conf.set('VERSION', version)
-conf.set('MAN_DATE', run_command('util/getversion.sh', '--man-date', check : true).stdout().strip())
+config_manfile = configuration_data()
+config_manfile.set('VERSION', version)
+config_manfile.set('MAN_DATE', run_command('util/getversion.sh', '--man-date', check : true).stdout().strip())
configure_file(
input : 'flashrom.8.tmpl',
output : 'flashrom.8',
- configuration : conf,
+ configuration : config_manfile,
install: true,
install_dir: join_paths(get_option('mandir'), 'man8'),
)
--
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: Icf24b9c47d4c7553f1ec045a9dfd3685b1376445
Gerrit-Change-Number: 70209
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-MessageType: newchange
Attention is currently required from: Edward O'Callaghan.
Hello build bot (Jenkins), Edward O'Callaghan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/70079
to look at the new patch set (#7).
Change subject: util/lint: Introduce linter for git sign-off-by line
......................................................................
util/lint: Introduce linter for git sign-off-by line
For compliance and to check if the commit message matches the
development guidelines, add a linter checking for the sign-off-by line
from the commit message. Also, hook it up to the test_build.sh script
which is used for CI builds.
These scripts were copied from the coreboot repository and were adjusted
so that they work for flashrom.
Change-Id: I03f1827803f8492d60a0a44174d5822c2265bfcb
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M test_build.sh
A util/lint/helper_functions.sh
A util/lint/lint-extended-020-signed-off-by
3 files changed, 93 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/70079/7
--
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Gerrit-Branch: master
Gerrit-Change-Id: I03f1827803f8492d60a0a44174d5822c2265bfcb
Gerrit-Change-Number: 70079
Gerrit-PatchSet: 7
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org>
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Attention is currently required from: Edward O'Callaghan.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70079 )
Change subject: util/lint: Introduce linter for git sign-off-by line
......................................................................
Set Ready For Review
--
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Gerrit-Branch: master
Gerrit-Change-Id: I03f1827803f8492d60a0a44174d5822c2265bfcb
Gerrit-Change-Number: 70079
Gerrit-PatchSet: 5
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Comment-Date: Thu, 01 Dec 2022 12:25:28 +0000
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Gerrit-MessageType: comment
Felix Singer has submitted this change. ( https://review.coreboot.org/c/flashrom/+/70039 )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: ichspi: Fix number of bytes for HW seq operations
......................................................................
ichspi: Fix number of bytes for HW seq operations
This patch fixes a potential issue where the SPI controller register
HSFC.FDBC (bits 24-29) value gets incorrectly calculated while passing
the `len` as `0` instead of `1`.
As per Intel EDS, `0b` in the FDBC represents 1 byte while `0x3f`
represents 64-bytes to be transferred. The number of bytes
transferred is the value of this field plus 1.
If we would like to transfer 1 byte then we need to set `0b` in
FDBC for operations like read, write, flash id as to account for
the `set byte count` hence, the `len` argument should be `1`.
Additionally, as per EDS, the FDBC field is ignored for any block
erase command.
BUG=b:258280679
TEST=Able to build flashrom and perform below operations on Google,
Rex and Google, Kano/Taeko.
During `--wp-disable` HW seq operation that requires 1 byte data
transfer.
HSFC.FDBC value while passing `len` as `0` = 0x3f (represents 64-byte)
HSFC.FDBC value while passing `len` as `1` = 0x0 (represents 1-byte)
Original-Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69789
Original-Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Original-Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
Original-Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com>
Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Change-Id: I5b911655649c693e576497520687d7810bbd3c54
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/70039
Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M ichspi.c
1 file changed, 56 insertions(+), 3 deletions(-)
Approvals:
build bot (Jenkins): Verified
Edward O'Callaghan: Looks good to me, approved
Anastasia Klimchuk: Looks good to me, but someone else must approve
diff --git a/ichspi.c b/ichspi.c
index 29dcd25..dd5a2c1 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1360,6 +1360,12 @@
/* Set up transaction parameters. */
hsfc |= hsfc_cycle;
+ /*
+ * The number of bytes transferred is the value of `FDBC` plus 1, hence,
+ * subtracted 1 from the length field.
+ * As per Intel EDS, `0b` in the FDBC represents 1 byte while `0x3f`
+ * represents 64-bytes to be transferred.
+ */
hsfc |= HSFC_FDBC_VAL(len - 1);
hsfc |= HSFC_FGO; /* start */
prettyprint_ich9_reg_hsfc(hsfc, ich_generation);
@@ -1399,7 +1405,7 @@
}
msg_pdbg("Reading Status register\n");
- if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_RD_STATUS, 0, len, ich_generation,
+ if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_RD_STATUS, 1, len, ich_generation,
hwseq_data->addr_mask)) {
msg_perr("Reading Status register failed\n!!");
return -1;
@@ -1422,7 +1428,7 @@
ich_fill_data(&value, len, ICH9_REG_FDATA0);
- if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_WR_STATUS, 0, len, ich_generation,
+ if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_WR_STATUS, 1, len, ich_generation,
hwseq_data->addr_mask)) {
msg_perr("Writing Status register failed\n!!");
return -1;
@@ -1518,7 +1524,7 @@
msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr);
- if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_BLOCK_ERASE, addr, 0, ich_generation,
+ if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_BLOCK_ERASE, addr, 1, ich_generation,
hwseq_data->addr_mask))
return -1;
return 0;
--
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Gerrit-Project: flashrom
Gerrit-Branch: 1.3.x
Gerrit-Change-Id: I5b911655649c693e576497520687d7810bbd3c54
Gerrit-Change-Number: 70039
Gerrit-PatchSet: 3
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Subrata Banik <subratabanik(a)google.com>
Gerrit-MessageType: merged
Felix Singer has submitted this change. ( https://review.coreboot.org/c/flashrom/+/69998 )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: ichspi: Clear Fast SPI HSFC register before HW seq operation
......................................................................
ichspi: Clear Fast SPI HSFC register before HW seq operation
This patch fixes a regression introduced with
commit 7ed1337309d3fe74f5af09520970f0f1d417399a (ichspi: Factor out
common hwseq_xfer logic into helpers).
The reason for the regression is ignoring the fact that the Fast SPI
controller MMIO register HSFC (0x06) might not hold the default zero
value before initiating the HW sequencing operation.
Having a `1b` value in the HSFC.FDBC (bits 24-29) field would represent
a byte that needs to be transfered.
While debugging the regression, we have observed that the default value
in the FDBC (prior to initiate any operation) is 0x3f (instead of
zero) which represents 64-byte transfer.
localhost ~ # iotools mmio_read32 0x92d16006
0x3f00
<Fast SPI MMIO BAR: 0x92d16000 and HSFC offset: 0x06>
FDBC offset during `--wp-disable` operation represents higher numbers of
bytes than the actual and eventually results in the error.
Additionally, dropped unused variable (struct hwseq_data *hwseq_data).
BUG=b:258280679
TEST=Able to build flashrom and perform below operations on Google, Rex
and Google, Kano/Taeko.
Without this patch:
HSFC register value inside ich_start_hwseq_xfer() before initiating
the HW seq operations: 0x3f00
HSFC register value inside ich_start_hwseq_xfer() during the HW seq
operations (Read Status): 0x3f11
With this patch:
HSFC register value inside ich_start_hwseq_xfer() before initiating
the HW seq operations: 0x0
HSFC register value inside ich_start_hwseq_xfer() during the HW seq
operations (Read Status): 0x11
Additionally, verified other HW sequencing operations (like read, write,
erase, read status, write status, read ID) working fine without any
error.
Original-Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69788
Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Original-Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
Original-Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com>
Change-Id: I4cc3f24f880d1d621f1f48a6e6b276449fa46f98
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/69998
Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M ichspi.c
1 file changed, 69 insertions(+), 4 deletions(-)
Approvals:
build bot (Jenkins): Verified
Edward O'Callaghan: Looks good to me, approved
Anastasia Klimchuk: Looks good to me, but someone else must approve
diff --git a/ichspi.c b/ichspi.c
index cd6e802..29dcd25 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1349,8 +1349,8 @@
uint32_t hsfc_cycle, uint32_t flash_addr, size_t len,
uint32_t addr_mask)
{
- uint16_t hsfc;
- struct hwseq_data *hwseq_data = get_hwseq_data_from_context(flash);
+ /* make sure HSFC register is cleared before initiate any operation */
+ uint16_t hsfc = 0;
/* Sets flash_addr in FADDR */
ich_hwseq_set_addr(flash_addr, addr_mask);
@@ -1359,8 +1359,6 @@
REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
/* Set up transaction parameters. */
- hsfc = REGREAD16(ICH9_REG_HSFC);
- hsfc &= ~hwseq_data->hsfc_fcycle; /* clear operation */
hsfc |= hsfc_cycle;
hsfc |= HSFC_FDBC_VAL(len - 1);
hsfc |= HSFC_FGO; /* start */
--
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Gerrit-Project: flashrom
Gerrit-Branch: 1.3.x
Gerrit-Change-Id: I4cc3f24f880d1d621f1f48a6e6b276449fa46f98
Gerrit-Change-Number: 69998
Gerrit-PatchSet: 3
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Subrata Banik <subratabanik(a)google.com>
Gerrit-MessageType: merged