November 2022 - flashrom-gerrit

[M] Change in flashrom[master]: flashchips.c: enable WP for 7 entries of MX chips
by Anastasia Klimchuk (Code Review) 19 Nov '22

19 Nov '22

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/66216 ) Change subject: flashchips.c: enable WP for 7 entries of MX chips ...................................................................... flashchips.c: enable WP for 7 entries of MX chips These weren't split: * MX25L3206E/MX25L3208E Tested: https://github.com/Dasharo/flashrom/pull/8 * MX25L6405 * MX25L6405D * MX25L6406E/MX25L6408E Tested: https://github.com/Dasharo/flashrom/pull/8 MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E/MX25L6473F was split into: * MX25L6436E/MX25L6445E/MX25L6465E - security register - WPS - tested: https://github.com/Dasharo/flashrom/pull/8 * MX25L6473E - security register - OTP TB bit in CONFIG/STATUS2 (0x15 opcode) - WPS * MX25L6473F - NO security register - OTP TB bit in CONFIG/STATUS2 (0x15 opcode) - NO WPS Change-Id: Ib3db9d39ffacd3e9e44de92c6cfb6c3ecc8615bd Tested-by: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66216 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashchips.c 1 file changed, 169 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index 2f328bb..9a9fd2e 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8918,7 +8918,7 @@ .page_size = 256, /* OTP: 64B total; enter 0xB1, exit 0xC1 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PREWB, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, .block_erasers = @@ -8945,6 +8945,13 @@ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, /* Fast read (0x0B) and dual I/O supported */ .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .cmp = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like CMP */ + }, + .decode_range = DECODE_RANGE_SPI25_BIT_CMP, }, { @@ -9171,6 +9178,12 @@ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { @@ -9207,6 +9220,13 @@ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, /* Fast read (0x0B), dual I/O read (0xBB) supported */ .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .cmp = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like CMP */ + }, + .decode_range = DECODE_RANGE_SPI25_BIT_CMP, }, { @@ -9220,7 +9240,7 @@ /* MX25L6406E supports SFDP */ /* OTP: 06E 64B total; enter 0xB1, exit 0xC1 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PREWB, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, .block_erasers = @@ -9247,11 +9267,18 @@ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, /* Fast read (0x0B), dual I/O read supported */ .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .cmp = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like CMP */ + }, + .decode_range = DECODE_RANGE_SPI25_BIT_CMP, }, { .vendor = "Macronix", - .name = "MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E/MX25L6473F", + .name = "MX25L6436E/MX25L6445E/MX25L6465E", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L6405, @@ -9259,7 +9286,54 @@ .page_size = 256, /* supports SFDP */ /* OTP: 512B total; enter 0xB1, exit 0xC1 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_SCUR, + .tested = TEST_OK_PREWB, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .wps = {SECURITY, 7, OTP}, /* This bit is set by WPSEL command */ + }, + .decode_range = DECODE_RANGE_SPI25_2X_BLOCK, + }, + + { + .vendor = "Macronix", + .name = "MX25L6473E", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L6405, + .total_size = 8192, + .page_size = 256, + /* supports SFDP */ + /* OTP: 512B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT2 | FEATURE_SCUR, .tested = TEST_OK_PREW, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, @@ -9287,6 +9361,61 @@ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {CONFIG, 3, OTP}, + .wps = {SECURITY, 7, OTP}, /* This bit is set by WPSEL command */ + }, + .decode_range = DECODE_RANGE_SPI25, + }, + + { + .vendor = "Macronix", + .name = "MX25L6473F", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L6405, + .total_size = 8192, + .page_size = 256, + /* supports SFDP */ + /* OTP: 512B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT2, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {CONFIG, 3, OTP}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { -- To view, visit https://review.coreboot.org/c/flashrom/+/66216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib3db9d39ffacd3e9e44de92c6cfb6c3ecc8615bd Gerrit-Change-Number: 66216 Gerrit-PatchSet: 11 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in flashrom[master]: flashchips.c: enable WP for MT25QL512, N25Q0{32,64}..{1,3}E
by Anastasia Klimchuk (Code Review) 19 Nov '22

19 Nov '22

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/66215 ) ( 9 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: flashchips.c: enable WP for MT25QL512, N25Q0{32,64}..{1,3}E ...................................................................... flashchips.c: enable WP for MT25QL512, N25Q0{32,64}..{1,3}E Change-Id: Ib0f3cb9516cea7bb678842a358a82099221e1ed9 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66215 Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M flashchips.c 1 file changed, 64 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index efe71d8..2f328bb 100644 --- a/flashchips.c +++ b/flashchips.c @@ -11258,6 +11258,17 @@ .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1700, 2000}, + .reg_bits = + { + /* + * There is also a volatile lock register per 64KiB sector, which is not + * mutually exclusive with BP-based protection. + */ + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { @@ -11292,6 +11303,17 @@ .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, + .reg_bits = + { + /* + * There is also a volatile lock register per 64KiB sector, which is not + * mutually exclusive with BP-based protection. + */ + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { @@ -11326,6 +11348,17 @@ .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1700, 2000}, + .reg_bits = + { + /* + * There is also a volatile lock register per 64KiB sector, which is not + * mutually exclusive with BP-based protection. + */ + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}}, + .tb = {STATUS1, 5, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { @@ -11360,6 +11393,17 @@ .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, + .reg_bits = + { + /* + * There is also a volatile lock register per 64KiB sector, which is not + * mutually exclusive with BP-based protection. + */ + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}}, + .tb = {STATUS1, 5, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { @@ -11999,6 +12043,13 @@ .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}}, + .tb = {STATUS1, 5, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { -- To view, visit https://review.coreboot.org/c/flashrom/+/66215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib0f3cb9516cea7bb678842a358a82099221e1ed9 Gerrit-Change-Number: 66215 Gerrit-PatchSet: 11 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in flashrom[master]: flashchips.c: enable WP for W25Q32.V, W25Q32.W and W25Q32JW...M
by Anastasia Klimchuk (Code Review) 19 Nov '22

19 Nov '22

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/66214 ) Change subject: flashchips.c: enable WP for W25Q32.V, W25Q32.W and W25Q32JW...M ...................................................................... flashchips.c: enable WP for W25Q32.V, W25Q32.W and W25Q32JW...M Split chips: * W25Q32.V -> W25Q32BV/W25Q32CV/W25Q32DV, W25Q32FV and W25Q32JV * W25Q32.W -> W25Q32BW/W25Q32CW/W25Q32DW, W25Q32FW and W25Q32JW...Q Change-Id: Id259c27dfa6c681bbadc73b3bd7559ad6a5865f4 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66214 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashchips.c 1 file changed, 265 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index cb993e0..efe71d8 100644 --- a/flashchips.c +++ b/flashchips.c @@ -17966,7 +17966,7 @@ { .vendor = "Winbond", - .name = "W25Q32.V", + .name = "W25Q32BV/W25Q32CV/W25Q32DV", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, .model_id = WINBOND_NEX_W25Q32_V, @@ -17974,7 +17974,7 @@ .page_size = 256, /* supports SFDP */ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT2, .tested = TEST_OK_PREW, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, @@ -18002,19 +18002,133 @@ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + .sec = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { .vendor = "Winbond", - .name = "W25Q32.W", + .name = "W25Q32FV", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q32_V, + .total_size = 4096, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | + FEATURE_WRSR_EXT2 | FEATURE_WRSR2 | FEATURE_WRSR3, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + .sec = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + .wps = {STATUS3, 2, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, + }, + + { + .vendor = "Winbond", + .name = "W25Q32JV", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q32_V, + .total_size = 4096, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | + FEATURE_WRSR_EXT2 | FEATURE_WRSR2 | FEATURE_WRSR3, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + .sec = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + .wps = {STATUS3, 2, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, + }, + + { + .vendor = "Winbond", + .name = "W25Q32BW/W25Q32CW/W25Q32DW", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, .model_id = WINBOND_NEX_W25Q32_W, .total_size = 4096, .page_size = 256, - /* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* OTP: 1024B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ /* QPI enable 0x38, disable 0xFF */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR_EXT2, .tested = TEST_OK_PREW, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, @@ -18042,6 +18156,120 @@ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, .voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */ + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + .sec = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, + }, + + { + .vendor = "Winbond", + .name = "W25Q32FW", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q32_W, + .total_size = 4096, + .page_size = 256, + /* OTP: 768B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | + FEATURE_WRSR_EXT2 | FEATURE_WRSR2 | FEATURE_WRSR3, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */ + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + .sec = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + .wps = {STATUS3, 2, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, + }, + + { + .vendor = "Winbond", + .name = "W25Q32JW...Q", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q32_W, + .total_size = 4096, + .page_size = 256, + /* OTP: 768B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | + FEATURE_WRSR_EXT2 | FEATURE_WRSR2 | FEATURE_WRSR3, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */ + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + .sec = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + .wps = {STATUS3, 2, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { @@ -18052,7 +18280,10 @@ .model_id = WINBOND_NEX_W25Q32JW_M, .total_size = 4096, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + /* OTP: 768B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | + FEATURE_WRSR2 | FEATURE_WRSR3 | FEATURE_WRSR_EXT2, .tested = TEST_OK_PREW, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, @@ -18080,6 +18311,17 @@ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, .voltage = {1700, 1950}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + .sec = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + .wps = {STATUS3, 2, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { -- To view, visit https://review.coreboot.org/c/flashrom/+/66214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id259c27dfa6c681bbadc73b3bd7559ad6a5865f4 Gerrit-Change-Number: 66214 Gerrit-PatchSet: 11 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in flashrom[master]: flashchips.c: enable WP for EN25QH32 and EN25QH64
by Anastasia Klimchuk (Code Review) 19 Nov '22

19 Nov '22

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/66213 ) Change subject: flashchips.c: enable WP for EN25QH32 and EN25QH64 ...................................................................... flashchips.c: enable WP for EN25QH32 and EN25QH64 Split chips: * EN25QH32 -> EN25QH32 and EN25QH32B * EN25QH64 -> EN25QH64 and EN25QH64A Unlike older revisions both newly added EN25QH32B and EN25QH64A support half block (32KiB) erase operation via 0x52 opcode. Change-Id: I759f0119346235ce0bddc78cde9c461495990c25 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66213 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashchips.c 1 file changed, 116 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index 88be1d1..cb993e0 100644 --- a/flashchips.c +++ b/flashchips.c @@ -5260,6 +5260,54 @@ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */ + }, + .decode_range = DECODE_RANGE_SPI25, + }, + + { + .vendor = "Eon", + .name = "EN25QH32B", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25QH32, + .total_size = 4096, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1536B total; enter 0x3A */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {1024 * 4096, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {1024 * 4096, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {2700, 3600}, }, { @@ -5298,6 +5346,54 @@ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */ + }, + .decode_range = DECODE_RANGE_SPI25_64K_BLOCK, + }, + + { + .vendor = "Eon", + .name = "EN25QH64A", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25QH64, + .total_size = 8192, + .page_size = 256, + /* supports SFDP */ + /* OTP: 512B total; enter 0x3A */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { { 8192 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { { 8192 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {2700, 3600}, }, { -- To view, visit https://review.coreboot.org/c/flashrom/+/66213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I759f0119346235ce0bddc78cde9c461495990c25 Gerrit-Change-Number: 66213 Gerrit-PatchSet: 11 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in flashrom[master]: flashchips.c: enable WP for 7 entries of MX chips
by Anastasia Klimchuk (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Nico Huber, Angel Pons, Nikolai Artemiev, Sergii Dmytruk. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/66216 ) Change subject: flashchips.c: enable WP for 7 entries of MX chips ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/66216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib3db9d39ffacd3e9e44de92c6cfb6c3ecc8615bd Gerrit-Change-Number: 66216 Gerrit-PatchSet: 10 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Sat, 19 Nov 2022 07:10:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[L] Change in flashrom[master]: flashchips.c: enable WP for W25Q32.V, W25Q32.W and W25Q32JW...M
by Anastasia Klimchuk (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Nico Huber, Angel Pons, Sergii Dmytruk. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/66214 ) Change subject: flashchips.c: enable WP for W25Q32.V, W25Q32.W and W25Q32JW...M ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/66214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id259c27dfa6c681bbadc73b3bd7559ad6a5865f4 Gerrit-Change-Number: 66214 Gerrit-PatchSet: 10 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Sat, 19 Nov 2022 07:08:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in flashrom[master]: flashchips.c: enable WP for EN25QH32 and EN25QH64
by Anastasia Klimchuk (Code Review) 19 Nov '22

19 Nov '22

Attention is currently required from: Nico Huber, Angel Pons, Sergii Dmytruk. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/66213 ) Change subject: flashchips.c: enable WP for EN25QH32 and EN25QH64 ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/66213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I759f0119346235ce0bddc78cde9c461495990c25 Gerrit-Change-Number: 66213 Gerrit-PatchSet: 10 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Sat, 19 Nov 2022 07:02:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in flashrom[master]: writeprotect_ranges.c: add more range functions
by Anastasia Klimchuk (Code Review) 19 Nov '22

19 Nov '22

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/66212 ) ( 9 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: writeprotect_ranges.c: add more range functions ...................................................................... writeprotect_ranges.c: add more range functions Not all chips follow the same pattern. There are differences in how CMP bit is treated or in block size used. Change-Id: Ied7b27be2ee2426af8f473432e2b01a290de2365 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66212 Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M include/chipdrivers.h M include/flash.h M writeprotect.c M writeprotect_ranges.c 4 files changed, 90 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Nikolai Artemiev: Looks good to me, but someone else must approve Anastasia Klimchuk: Looks good to me, approved diff --git a/include/chipdrivers.h b/include/chipdrivers.h index 3b07afe..34e3af8 100644 --- a/include/chipdrivers.h +++ b/include/chipdrivers.h @@ -216,5 +216,8 @@ /* writeprotect_ranges.c */ void decode_range_spi25(size_t *start, size_t *len, const struct wp_bits *, size_t chip_len); +void decode_range_spi25_64k_block(size_t *start, size_t *len, const struct wp_bits *, size_t chip_len); +void decode_range_spi25_bit_cmp(size_t *start, size_t *len, const struct wp_bits *, size_t chip_len); +void decode_range_spi25_2x_block(size_t *start, size_t *len, const struct wp_bits *, size_t chip_len); #endif /* !__CHIPDRIVERS_H__ */ diff --git a/include/flash.h b/include/flash.h index 23222c7..b4b56fe 100644 --- a/include/flash.h +++ b/include/flash.h @@ -224,8 +224,11 @@ struct wp_bits; enum decode_range_func { - NO_DECODE_RANGE_FUNC = 0, /* 0 indicates no range decode funciton is set. */ + NO_DECODE_RANGE_FUNC = 0, /* 0 indicates no range decode function is set. */ DECODE_RANGE_SPI25 = 1, + DECODE_RANGE_SPI25_64K_BLOCK = 2, + DECODE_RANGE_SPI25_BIT_CMP = 3, + DECODE_RANGE_SPI25_2X_BLOCK = 4, }; typedef void (decode_range_func_t)(size_t *start, size_t *len, const struct wp_bits *, size_t chip_len); diff --git a/writeprotect.c b/writeprotect.c index 1ac0c1a..38ac997 100644 --- a/writeprotect.c +++ b/writeprotect.c @@ -211,6 +211,9 @@ { switch (chip->decode_range) { case DECODE_RANGE_SPI25: return &decode_range_spi25; + case DECODE_RANGE_SPI25_64K_BLOCK: return &decode_range_spi25_64k_block; + case DECODE_RANGE_SPI25_BIT_CMP: return &decode_range_spi25_bit_cmp; + case DECODE_RANGE_SPI25_2X_BLOCK: return &decode_range_spi25_2x_block; /* default: total function, 0 indicates no decode range function set. */ case NO_DECODE_RANGE_FUNC: return NULL; }; diff --git a/writeprotect_ranges.c b/writeprotect_ranges.c index dacce32..45678f2 100644 --- a/writeprotect_ranges.c +++ b/writeprotect_ranges.c @@ -17,11 +17,11 @@ #include "writeprotect.h" #include "chipdrivers.h" -/* - * Protection range calculation that works with many common SPI flash chips. - */ -void decode_range_spi25(size_t *start, size_t *len, const struct wp_bits *bits, size_t chip_len) +static void decode_range_generic(size_t *start, size_t *len, const struct wp_bits *bits, size_t chip_len, + bool fixed_block_len, bool apply_cmp_to_bp, int coeff_offset) { + const bool cmp = bits->cmp_bit_present && bits->cmp == 1; + /* Interpret BP bits as an integer */ size_t bp = 0; size_t bp_max = 0; @@ -31,6 +31,15 @@ bp_max |= 1 << i; } + /* + * Most chips: the CMP bit only negates the range. + * + * Some MX chips: the CMP bit negates the BP bits and the range. + * (CMP bit is often the MSB BP bit in such chips.) + */ + if (cmp && apply_cmp_to_bp) + bp ^= bp_max; + if (bp == 0) { /* Special case: all BP bits are 0 => no write protection */ *len = 0; @@ -40,14 +49,14 @@ } else { /* * Usual case: the BP bits encode a coefficient in the form - * `coeff = 2 ** (bp - 1)`. + * `coeff = 2 ** (bp - offset)` where `offset == 1`. * * The range's length is given by multiplying the coefficient * by a base unit, usually a 4K sector or a 64K block. */ - size_t coeff = 1 << (bp - 1); - size_t max_coeff = 1 << (bp_max - 2); + size_t coeff = 1 << (bp - coeff_offset); + size_t max_coeff = 1 << (bp_max - coeff_offset - 1); size_t sector_len = 4 * KiB; size_t default_block_len = 64 * KiB; @@ -62,14 +71,19 @@ } else { /* * SEC=0 or is not present, protect blocks. - * + */ + size_t block_len = default_block_len; + + /* * With very large chips, the 'block' size can be * larger than 64K. This occurs when a larger block * size is needed so that half the chip can be * protected by the maximum possible coefficient. */ - size_t min_block_len = chip_len / 2 / max_coeff; - size_t block_len = max(min_block_len, default_block_len); + if (!fixed_block_len) { + size_t min_block_len = chip_len / 2 / max_coeff; + block_len = max(min_block_len, default_block_len); + } *len = min(block_len * coeff, chip_len); } @@ -79,7 +93,7 @@ bool protect_top = bits->tb_bit_present ? (bits->tb == 0) : 1; /* Apply CMP bit */ - if (bits->cmp_bit_present && bits->cmp == 1) { + if (cmp) { *len = chip_len - *len; protect_top = !protect_top; } @@ -90,3 +104,41 @@ else *start = 0; } + +/* + * Protection range calculation that works with many common SPI flash chips. + */ +void decode_range_spi25(size_t *start, size_t *len, const struct wp_bits *bits, size_t chip_len) +{ + decode_range_generic(start, len, bits, chip_len, + /*fixed_block_len=*/false, /*apply_cmp_to_bp=*/false, /*coeff_offset=*/1); +} + +/* + * Do not adjust block size to be able to fill half of the chip. + */ +void decode_range_spi25_64k_block(size_t *start, size_t *len, const struct wp_bits *bits, size_t chip_len) +{ + decode_range_generic(start, len, bits, chip_len, + /*fixed_block_len=*/true, /*apply_cmp_to_bp=*/false, /*coeff_offset=*/1); +} + +/* + * Inverts BP bits when CMP is set and treats all ones in BP bits as a request to protect whole chip regardless + * of the CMP bit. + */ +void decode_range_spi25_bit_cmp(size_t *start, size_t *len, const struct wp_bits *bits, size_t chip_len) +{ + decode_range_generic(start, len, bits, chip_len, + /*fixed_block_len=*/false, /*apply_cmp_to_bp=*/true, /*coeff_offset=*/1); +} + +/* + * This multiplies coefficient by 2. To be used with chips which have more BP bits than needed, such that the + * most significant BP bit effectively acts as "protect whole chip" flag. + */ +void decode_range_spi25_2x_block(size_t *start, size_t *len, const struct wp_bits *bits, size_t chip_len) +{ + decode_range_generic(start, len, bits, chip_len, + /*fixed_block_len=*/false, /*apply_cmp_to_bp=*/false, /*coeff_offset=*/0); +} -- To view, visit https://review.coreboot.org/c/flashrom/+/66212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ied7b27be2ee2426af8f473432e2b01a290de2365 Gerrit-Change-Number: 66212 Gerrit-PatchSet: 11 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-MessageType: merged

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[M] Change in flashrom[master]: spi25_statusreg: support reading/writing configuration register
by Anastasia Klimchuk (Code Review) 19 Nov '22

19 Nov '22

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/66211 ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: spi25_statusreg: support reading/writing configuration register ...................................................................... spi25_statusreg: support reading/writing configuration register One more variation of registers. This one is read via a separate RDCR command, but written as if it's SR2 using WRSR_EXT2. Change-Id: I45f9afcc31f1928ef6263a749596380082963de4 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66211 Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M include/flash.h M include/spi.h M spi25_statusreg.c 3 files changed, 52 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved Nikolai Artemiev: Looks good to me, but someone else must approve diff --git a/include/flash.h b/include/flash.h index 197c11e..23222c7 100644 --- a/include/flash.h +++ b/include/flash.h @@ -161,6 +161,9 @@ */ #define FEATURE_SCUR (1 << 24) +/* Whether chip has configuration register (RDCR/WRSR_EXT2 commands) */ +#define FEATURE_CFGR (1 << 25) + #define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff) #define UNERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0xff : 0x00) @@ -196,6 +199,7 @@ STATUS2, STATUS3, SECURITY, + CONFIG, MAX_REGISTERS }; diff --git a/include/spi.h b/include/spi.h index c77866c..505aecd 100644 --- a/include/spi.h +++ b/include/spi.h @@ -177,6 +177,11 @@ #define JEDEC_WRSCUR_OUTSIZE 0x01 #define JEDEC_WRSCUR_INSIZE 0x00 +/* Read Configuration Register */ +#define JEDEC_RDCR 0x15 +#define JEDEC_RDCR_OUTSIZE 0x01 +#define JEDEC_RDCR_INSIZE 0x01 + /* Enter 4-byte Address Mode */ #define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7 diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 2859b23..b178b2e 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -107,6 +107,23 @@ */ msg_cerr("Cannot write SECURITY: unsupported by design\n"); return 1; + case CONFIG: + /* + * This one is read via a separate command, but written as if it's SR2 + * in FEATURE_WRSR_EXT2 case of WRSR command. + */ + if (feature_bits & FEATURE_CFGR) { + write_cmd[0] = JEDEC_WRSR; + if (spi_read_register(flash, STATUS1, &write_cmd[1])) { + msg_cerr("Writing CONFIG failed: failed to read SR1 for writeback.\n"); + return 1; + } + write_cmd[2] = value; + write_cmd_len = 3; + break; + } + msg_cerr("Cannot write CONFIG: unsupported by chip\n"); + return 1; default: msg_cerr("Cannot write register: unknown register\n"); return 1; @@ -209,6 +226,13 @@ } msg_cerr("Cannot read SECURITY: unsupported by chip\n"); return 1; + case CONFIG: + if (feature_bits & FEATURE_CFGR) { + read_cmd = JEDEC_RDCR; + break; + } + msg_cerr("Cannot read CONFIG: unsupported by chip\n"); + return 1; default: msg_cerr("Cannot read register: unknown register\n"); return 1; -- To view, visit https://review.coreboot.org/c/flashrom/+/66211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I45f9afcc31f1928ef6263a749596380082963de4 Gerrit-Change-Number: 66211 Gerrit-PatchSet: 10 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in flashrom[master]: spi25_statusreg.c: support reading security register
by Anastasia Klimchuk (Code Review) 19 Nov '22

19 Nov '22

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/59709 ) ( 31 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: spi25_statusreg.c: support reading security register ...................................................................... spi25_statusreg.c: support reading security register Not to be confused with "secure registers" of OTP. Security register is a dedicated status register for security-related bits. You don't write its value directly, issuing special write commands with no data set separate OTP bits to 1 automatically (WRSCUR, WPSEL commands). No WREN is necessary, but at least some datasheets indicate BUSY state after those write commands. Unlike cases where OTP bit is part of SR and can only be written while in OTP mode, security register can only be written outside of the mode. The register is found in at least these chips by Macronix: * MX25L6436E * MX25L6445E * MX25L6465E * MX25L6473E Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59709 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M include/flash.h M include/spi.h M spi25_statusreg.c 3 files changed, 63 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Edward O'Callaghan: Looks good to me, approved Nikolai Artemiev: Looks good to me, but someone else must approve diff --git a/include/flash.h b/include/flash.h index ea8e25b..197c11e 100644 --- a/include/flash.h +++ b/include/flash.h @@ -155,6 +155,12 @@ #define FEATURE_WRSR_EXT3 ((1 << 22) | FEATURE_WRSR_EXT2) #define FEATURE_WRSR3 (1 << 23) +/* + * Whether chip has security register (RDSCUR/WRSCUR commands). + * Not to be confused with "secure registers" of OTP. + */ +#define FEATURE_SCUR (1 << 24) + #define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff) #define UNERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0xff : 0x00) @@ -189,6 +195,7 @@ STATUS1, STATUS2, STATUS3, + SECURITY, MAX_REGISTERS }; diff --git a/include/spi.h b/include/spi.h index 9b38cab..c77866c 100644 --- a/include/spi.h +++ b/include/spi.h @@ -167,6 +167,16 @@ #define JEDEC_WRSR3_OUTSIZE 0x02 #define JEDEC_WRSR3_INSIZE 0x00 +/* Read Security Register */ +#define JEDEC_RDSCUR 0x2b +#define JEDEC_RDSCUR_OUTSIZE 0x01 +#define JEDEC_RDSCUR_INSIZE 0x01 + +/* Write Security Register */ +#define JEDEC_WRSCUR 0x2f +#define JEDEC_WRSCUR_OUTSIZE 0x01 +#define JEDEC_WRSCUR_INSIZE 0x00 + /* Enter 4-byte Address Mode */ #define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7 diff --git a/spi25_statusreg.c b/spi25_statusreg.c index d0ce859..2859b23 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -100,6 +100,13 @@ } msg_cerr("Cannot write SR3: unsupported by chip\n"); return 1; + case SECURITY: + /* + * Security register doesn't have a normal write operation. Instead, + * there are separate commands that set individual OTP bits. + */ + msg_cerr("Cannot write SECURITY: unsupported by design\n"); + return 1; default: msg_cerr("Cannot write register: unknown register\n"); return 1; @@ -195,6 +202,13 @@ } msg_cerr("Cannot read SR3: unsupported by chip\n"); return 1; + case SECURITY: + if (feature_bits & FEATURE_SCUR) { + read_cmd = JEDEC_RDSCUR; + break; + } + msg_cerr("Cannot read SECURITY: unsupported by chip\n"); + return 1; default: msg_cerr("Cannot read register: unknown register\n"); return 1; -- To view, visit https://review.coreboot.org/c/flashrom/+/59709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae Gerrit-Change-Number: 59709 Gerrit-PatchSet: 33 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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