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Change subject: [RFC][OTP] libflashrom,otp: add OTP regions management API
......................................................................
[RFC][OTP] libflashrom,otp: add OTP regions management API
This implements both OTP mode and secure registers variants. Support for
chips that have security registers is added in later commits.
Change-Id: Idf222b20973bf99a4e65e0fa8e464232969fd7e1
Signed-off-by: Hatim Kanchwala <hatim at hatimak.me>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M Makefile
M libflashrom.h
M meson.build
A otp.c
M otp.h
M writeprotect.h
6 files changed, 514 insertions(+), 1 deletion(-)
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Hello build bot (Jenkins), Nico Huber, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/59402
to look at the new patch set (#18).
Change subject: [RFC][OTP] spi: add functions for OTP regions
......................................................................
[RFC][OTP] spi: add functions for OTP regions
These are functions for entering/leaving OTP mode and
reading/writing/erasing secure registers.
Also introduces part of the structure that describes OTP, because new
code uses it.
========================================================================
This and other patches marked [OTP] resurrect the work of Hatim
Kanchwala aimed at adding OTP support to flashrom:
https://blogs.coreboot.org/blog/author/hatim/
This chain of patches is based on my WP tests patches (starts at
CB:59071), which in turn depend on the set of patches that introduce
write-protect support (start at CB:58474).
Due to WP patches not being included in the chain, there are minor
modifications here caused by rebasing. This will go away once those
changes land on master.
========================================================================
Change-Id: Ic33e2c1de8b0ca02df9118218a663ce63826f339
Signed-off-by: Hatim Kanchwala <hatim at hatimak.me>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M chipdrivers.h
M flash.h
A otp.h
M spi.h
M spi25.c
5 files changed, 168 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/02/59402/18
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#24).
Change subject: tests: test write protection
......................................................................
tests: test write protection
Tests both WP implementation and its emulation in dummy programmer.
Change-Id: I49af7f6d173eb4c56c22d80b01a473b8c499c0f8
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
A tests/chip_wp.c
M tests/meson.build
M tests/tests.c
M tests/tests.h
4 files changed, 318 insertions(+), 0 deletions(-)
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Hello build bot (Jenkins), Nico Huber, Angel Pons, Anastasia Klimchuk, Nikolai Artemiev,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/59074
to look at the new patch set (#23).
Change subject: dummyflasher: enforce write protection for W25Q128FV
......................................................................
dummyflasher: enforce write protection for W25Q128FV
Start taking bits related to write protection into account.
Also add "hwwp" parameter for dummy programmer that sets state of WP
pin (not inverted value).
dummyflasher doesn't store state of the chip between runs and flashrom
allows running only one command, so testing WP in this way is limited.
However, WP options can be combined with other operations and are
executed prior to them, so certain scenarios can be checked.
List possible ranges:
flashrom -p dummy:emulate=W25Q128FV,hwwp=yes --wp-list
Set a particular range and check status is correct:
flashrom -p dummy:emulate=W25Q128FV,hwwp=yes \
--wp-enable \
--wp-range=0x00100000,0x00f00000 \
--wp-status
Enable write protection and try erasing/writing (erasing here):
# this fails
flashrom -p dummy:emulate=W25Q128FV,hwwp=yes \
--wp-range=0,0x00c00000 \
--wp-enable \
--erase
Write protecting empty range has no effect:
# this succeeds
flashrom -p dummy:emulate=W25Q128FV,hwwp=yes \
--wp-range=0,0 \
--wp-enable \
--erase
Change-Id: I9fd1417f941186391bd213bd355530143c8f04a0
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M dummyflasher.c
M flashrom.8.tmpl
2 files changed, 157 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/74/59074/23
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#23).
Change subject: dummyflasher: emulate SR2 and SR3 for W25Q128FV
......................................................................
dummyflasher: emulate SR2 and SR3 for W25Q128FV
Enable emulation of SR2 and SR3 for W25Q128FV and provide logic for
updating them (masks of read-only bits that can't be set from outside).
Change-Id: I79f9b4a0b604663d3288ad70dcbe3ea4075dede5
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M dummyflasher.c
1 file changed, 26 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/59073/23
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#23).
Change subject: dummyflasher: add SR2 and SR3 emulation harness
......................................................................
dummyflasher: add SR2 and SR3 emulation harness
Prepare everything for emulating SR2 and SR3 for chips that have it.
This is needed for accessing SRP1 and WPS bits which are involved in
write protection. The emulated register doesn't affect anything yet
and will be tested by write-protection tests.
Change-Id: I177ae3f068f03380f5b3941d9996a07205672e59
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M dummyflasher.c
M flashrom.8.tmpl
2 files changed, 109 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/72/59072/23
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#19).
Change subject: flashchips: enable write-protection for W25Q{64,128}.V
......................................................................
flashchips: enable write-protection for W25Q{64,128}.V
Configuration for W25Q64 was tested on hardware (W25Q64FV).
Emulation of W25Q128 in dummyflasher will be extended to support WP.
Haven't tested this one on hardware, but it's the same configuration as
for W25Q64 except that it has WPS.
W25Q64.V chip was split into W25Q64BV/W25Q64CV/W25Q64FV (no SR3 and WPS)
and W25Q64JV (SR3 and WPS).
Change-Id: Iccb69a8d3a0dd2192e2c938caddaf07b1889ed35
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M flashchips.c
1 file changed, 75 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/71/59071/19
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Hello build bot (Jenkins), Nico Huber, Nikolai Artemiev, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: writeprotect: add WPS bit and set it to zero
......................................................................
writeprotect: add WPS bit and set it to zero
Handle WPS by always setting it to zero until proper support for it is
implemented.
Change-Id: I2c26ec65d64a3b6fb1f1a73690bc771415db2744
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M flash.h
M writeprotect.c
2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/31/60231/3
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Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59528 )
Change subject: spi25_statusreg: inline spi_write_register_flag()
......................................................................
Patch Set 21:
(1 comment)
File spi25_statusreg.c:
https://review.coreboot.org/c/flashrom/+/59528/comment/8a816b03_f054947d
PS21, Line 110: /* WRSR performs a self-timed erase before the changes take effect.
: * This may take 50-85 ms in most cases, and some chips apparently
: * allow running RDSR only once. Therefore pick an initial delay of
: * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed.
: */
: int i = 0;
: programmer_delay(100 * 1000);
: while (spi_read_status_register(flash) & SPI_SR_WIP) {
: if (++i > 490) {
: msg_cerr("Error: WIP bit after WRSR never cleared\n");
: return TIMEOUT_ERROR;
: }
: programmer_delay(10 * 1000);
: }
: return 0;
This undoes changes to the waiting loop recently made in CB:58475.
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Hello build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#10).
Change subject: Makefile: merge compiler, hwlibs, features targets into config target
......................................................................
Makefile: merge compiler, hwlibs, features targets into config target
These targets are all called together. No need to have them individual.
Change-Id: Ic76f923bca2beb6f95b8ea0cced4569b07e9b9ba
Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com>
---
M Makefile
1 file changed, 12 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/07/60107/10
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