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Change subject: linux_mtd: check ioctl() return value properly
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
Hmmm, git history says this code came from ChromiumOS 😄
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Change subject: writeprotect: print chip range truth table for debugging
......................................................................
Patch Set 12:
(1 comment)
File writeprotect.c:
https://review.coreboot.org/c/flashrom/+/59909/comment/0225581f_f6535de3
PS5, Line 283: dbg
> IMO, `dbg2` or even `spew` would fit better here. I guess this can […]
Done, I went with msg_gspew(). For chips with 3BP bits + SEC + TB + CMP there'd be 64 lines.
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Hello build bot (Jenkins), Nico Huber, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#12).
Change subject: writeprotect: print chip range truth table for debugging
......................................................................
writeprotect: print chip range truth table for debugging
Make it easier to add new chips and debug range decoding functions by
printing a complete truth table of config bits / ranges.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-list -V
BRANCH=none
Change-Id: I2cda441229ffdcabff27906f7804efba82baa6bc
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M writeprotect.c
1 file changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/09/59909/12
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
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Change subject: spi25_statusreg: delete read_status_register()
......................................................................
spi25_statusreg: delete read_status_register()
BUG=b:195381327,b:153800563
TEST=builds
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---
M chipdrivers.h
M it87spi.c
M s25f.c
M spi25.c
M spi25_statusreg.c
5 files changed, 150 insertions(+), 53 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/29/59529/21
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk,
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Change subject: spi25_statusreg: inline spi_write_register_flag()
......................................................................
spi25_statusreg: inline spi_write_register_flag()
Creating the entire SPI command that should be sent to the chip in
spi_write_register() is simpler than splitting it across two functions
that have to pass multiple parameters between them.
Additionally, having separate spi_write_register_flag() function
provided little benefit, as it was only ever called from
spi_write_register().
BUG=b:195381327,b:153800563
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---
M spi25_statusreg.c
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git pull ssh://review.coreboot.org:29418/flashrom refs/changes/28/59528/20
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Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58481 )
Change subject: libflashrom,writeprotect: add flashrom_wp_get_ranges()
......................................................................
Patch Set 29:
(10 comments)
File libflashrom.h:
https://review.coreboot.org/c/flashrom/+/58481/comment/6abe25c9_fa070678
PS23, Line 137: #define FLASHROM_WP_MAX_RANGES 128
> Should we use dynamic allocation instead?
Done
https://review.coreboot.org/c/flashrom/+/58481/comment/ea09f326_7547bf65
PS23, Line 143: size_t
> Technically `size_t` is supposed to specify a byte count. It's often […]
It's nice that size_t is guaranteed to be large enough to represent the number of elements in any array though. Although size_t's intended use is for representing the size of an object in bytes, I don't think that should keep us from using it for somewhere else where it's well suited.
File writeprotect.c:
https://review.coreboot.org/c/flashrom/+/58481/comment/07e8e40a_724fb596
PS23, Line 187: preferred
> What is preferred and why?
For choosing one range encoding over another it's pretty much arbitrary. Usually the only ranges that have multiple encodings either span the entire flash or are completely empty. E.g. TB and SEC have no affect on them. In that case TB/SEC are just set to 0.
I've removed preferred from the description since it was misleading.
https://review.coreboot.org/c/flashrom/+/58481/comment/9a67f579_b5c10f3c
PS23, Line 233: TB in a OTP register
> Please mention the chip where you have seen something like this. Sometimes […]
Done
https://review.coreboot.org/c/flashrom/+/58481/comment/54d9ee3d_f5cc0e35
PS23, Line 234: perserved
> p*re*served
Done
https://review.coreboot.org/c/flashrom/+/58481/comment/d5ac52ce_86fee205
PS23, Line 237: 20
> ARRAY_SIZE(bits->bp) + 1 /* TB */ + 1 /* SEC */ + 1 /* CMP */ ?
Done
https://review.coreboot.org/c/flashrom/+/58481/comment/88d3b7dc_b1ce3d8e
PS23, Line 240: can_write_bit(bits->bp[i])
> This would stop at the first not writable bit and skip further writable […]
Done
https://review.coreboot.org/c/flashrom/+/58481/comment/bf63877d_b27d14d5
PS23, Line 255: for (uint32_t range_index = 0; range_index < *count; range_index++) {
> Please check that the destination arrays don't overflow (wouldn't […]
Done
https://review.coreboot.org/c/flashrom/+/58481/comment/fbb2de56_a1fff68c
PS23, Line 255: 32
> Why 32?
Changed to size_t.
https://review.coreboot.org/c/flashrom/+/58481/comment/d7afba92_d3026f76
PS23, Line 308: struct wp_range_cfg_pair range_cfg_pairs[FLASHROM_WP_MAX_RANGES];
> Not on the stack, please. Flashrom sometimes runs in embedded environments.
Done
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58481
to look at the new patch set (#29).
Change subject: libflashrom,writeprotect: add flashrom_wp_get_ranges()
......................................................................
libflashrom,writeprotect: add flashrom_wp_get_ranges()
Generate list of available ranges by enumerating all possible values
that range bits (BPx, TB, ...) can take and using the chip's range
decoding function to get the range that is selected by each one.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-list
BRANCH=none
Change-Id: Id51f038f03305c8536d80313e52f77d27835f34d
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M libflashrom.h
M writeprotect.c
2 files changed, 194 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/81/58481/29
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