flashrom-gerrit January 2022

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Change in flashrom[master]: chipset_enable.c: Add TGP-H IDs
by Angel Pons (Code Review) 05 Jan '22

05 Jan '22

Attention is currently required from: Tim Crawford, Nico Huber. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/57533 ) Change subject: chipset_enable.c: Add TGP-H IDs ...................................................................... Patch Set 7: Code-Review+2 (1 comment) Patchset: PS7: Doing a rebase before submitting just in case. -- To view, visit https://review.coreboot.org/c/flashrom/+/57533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I96f63253d42578151f99dcbb42347afecc03f49d Gerrit-Change-Number: 57533 Gerrit-PatchSet: 7 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 05 Jan 2022 16:26:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: hwaccess_x86_msr: fix build for FreeBSD
by Nico Huber (Code Review) 05 Jan '22

05 Jan '22

Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/60342 ) Change subject: hwaccess_x86_msr: fix build for FreeBSD ...................................................................... hwaccess_x86_msr: fix build for FreeBSD Add missing includes for FreeBSD Change-Id: I2045345878392436b0ea4d6bd4f2896edc645673 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/60342 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M hwaccess_x86_msr.c 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Idwer Vollering: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/hwaccess_x86_msr.c b/hwaccess_x86_msr.c index fa7df72..79cf2f8 100644 --- a/hwaccess_x86_msr.c +++ b/hwaccess_x86_msr.c @@ -204,6 +204,13 @@ } #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) +#include <stdint.h> +#include <stdlib.h> +#include <errno.h> +#include <fcntl.h> +#include <string.h> +#include <unistd.h> + #include <sys/ioctl.h> typedef struct { 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/flashrom/+/60342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2045345878392436b0ea4d6bd4f2896edc645673 Gerrit-Change-Number: 60342 Gerrit-PatchSet: 3 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in flashrom[master]: chipset_enable.c: Add TGP-H IDs
by Benjamin Doron (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Tim Crawford, Nico Huber. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/57533 ) Change subject: chipset_enable.c: Add TGP-H IDs ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/flashrom/+/57533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I96f63253d42578151f99dcbb42347afecc03f49d Gerrit-Change-Number: 57533 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 04 Jan 2022 22:55:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: libflashrom,writeprotect: add flashrom_wp_{read,write}_chip_config()
by Nikolai Artemiev (Code Review) 04 Jan '22

04 Jan '22

Attention is currently required from: Nico Huber, Edward O'Callaghan, Anastasia Klimchuk, Sergii Dmytruk. Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58479 ) Change subject: libflashrom,writeprotect: add flashrom_wp_{read,write}_chip_config() ...................................................................... Patch Set 23: (1 comment) Patchset: PS22: > Disregard typo above, start and len shouldn't be pointers in flashrom_wp_protect_flash(). […] Passing an abstract configuration structure to WP functions is probably a better option than the interface in my previous comment. Something like: ``` struct flashrom_wp_cfg { enum flashrom_wp_mode { WP_MODE_DISABLED, WP_MODE_HARDWARE } prot_mode; struct flashrom_wp_range { chipsize_t start, len; } prot_range; }; int flashrom_wp_get_cfg(struct flashrom_wp_cfg *, struct flashrom_flashctx *); int flashrom_wp_set_cfg(struct flashrom_flashctx *, struct flashrom_wp_cfg); ``` Then libflashrom users just populate the structure with the settings they want and the WP code will write them to the chip if it's possible to do so. Direct SPI WP will be able to write any configuration, so won't lose any functionality that we have right now with the individual {get,set}_wp_{mode,range} functions. And linux_mtd WP can just return an error if it's not possible to write the config (i.e. it doesn't map to a MTD ioctl). -- To view, visit https://review.coreboot.org/c/flashrom/+/58479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3ad25708c3321b8fb0216c3eaf6ffc07616537ad Gerrit-Change-Number: 58479 Gerrit-PatchSet: 23 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Tue, 04 Jan 2022 22:44:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: comment

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Change in flashrom[master]: Add Elkhart Lake support
by Werner Zeh (Code Review) 03 Jan '22

03 Jan '22

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/60711 ) Change subject: Add Elkhart Lake support ...................................................................... Add Elkhart Lake support Elkhart Lake has a chipset called Mule Creek Canyon which is quite compatible with 300 series chipsets. There are a few differences though, e.g. different encoding for the SPI clock values for read and write in the FLCOMP register. In addition Elkhart Lake has a new PCI device ID for the SPI controller which is added, too. TEST=Read and flash complete flash on Siemens MC EHL1 Change-Id: I711e39a3ec9cd7098389231eaa1cb864d615a475 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M chipset_enable.c M ich_descriptors.c M ichspi.c M programmer.h M util/ich_descriptors_tool/ich_descriptors_tool.c 5 files changed, 42 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/11/60711/1 diff --git a/chipset_enable.c b/chipset_enable.c index 2e4bb1e..8528cfc 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -601,6 +601,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_ELKHART_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: reg_name = "BIOS_SPI_BC"; @@ -704,6 +705,7 @@ boot_straps = boot_straps_pch8_lp; break; case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_ELKHART_LAKE: boot_straps = boot_straps_pch500; break; case CHIPSET_APOLLO_LAKE: @@ -737,6 +739,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_ELKHART_LAKE: bbs = (gcs >> 6) & 0x1; break; default: @@ -987,6 +990,11 @@ return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_500_SERIES_TIGER_POINT); } +static int enable_flash_mcc(struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_ELKHART_LAKE); +} + static int enable_flash_apl(struct pci_dev *const dev, const char *const name) { return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE); @@ -2101,6 +2109,7 @@ {0x8086, 0x5af0, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, {0x8086, 0x3197, B_S, NT, "Intel", "Gemini Lake", enable_flash_glk}, {0x8086, 0x31e8, B_S, DEP, "Intel", "Gemini Lake", enable_flash_glk}, + {0x8086, 0x4b24, B_S, DEP, "Intel", "Elkhart Lake", enable_flash_mcc}, {0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300}, {0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300}, {0x8086, 0xa305, B_S, DEP, "Intel", "Z390", enable_flash_pch300}, diff --git a/ich_descriptors.c b/ich_descriptors.c index 56a3c67..3d253a1 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -46,6 +46,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_ELKHART_LAKE: return 16; case CHIPSET_100_SERIES_SUNRISE_POINT: return 10; @@ -72,6 +73,7 @@ case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_ELKHART_LAKE: if (cont->NM <= MAX_NUM_MASTERS) return cont->NM; break; @@ -109,7 +111,7 @@ "8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg", "9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point", "C620 series Lewisburg", "300 series Cannon Point", "400 series Comet Point", - "500 series Tiger Point", "Apollo Lake", "Gemini Lake", + "500 series Tiger Point", "Apollo Lake", "Gemini Lake", "Elkhart Lake", }; if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names)) cs = 0; @@ -205,7 +207,8 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: - case CHIPSET_GEMINI_LAKE: { + case CHIPSET_GEMINI_LAKE: + case CHIPSET_ELKHART_LAKE: { uint8_t size_enc; if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; @@ -224,7 +227,7 @@ static const char *pprint_freq(enum ich_chipset cs, uint8_t value) { - static const char *const freq_str[4][8] = { { + static const char *const freq_str[5][8] = { { "20 MHz", "33 MHz", "reserved", @@ -260,6 +263,15 @@ "reserved", "14 MHz", "reserved" + }, { + "reserved", + "50 MHz", + "reserved", + "reserved", + "33 MHz", + "20 MHz", + "reserved", + "reserved", }}; switch (cs) { @@ -289,6 +301,8 @@ return freq_str[2][value]; case CHIPSET_500_SERIES_TIGER_POINT: return freq_str[3][value]; + case CHIPSET_ELKHART_LAKE: + return freq_str[4][value]; case CHIPSET_ICH_UNKNOWN: default: return "unknown"; @@ -334,6 +348,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_ELKHART_LAKE: has_flill1 = true; break; default: @@ -513,7 +528,7 @@ desc->master.mstr[i].write & (1 << j) ? 'w' : ' '); msg_pdbg2("\n"); } - } else if (cs == CHIPSET_APOLLO_LAKE || cs == CHIPSET_GEMINI_LAKE) { + } else if (cs == CHIPSET_APOLLO_LAKE || cs == CHIPSET_GEMINI_LAKE || cs == CHIPSET_ELKHART_LAKE) { const char *const master_names[] = { "BIOS", "TXE", }; if (nm > (ssize_t)ARRAY_SIZE(master_names)) { msg_pdbg2("%s: number of masters too high (%d).\n", __func__, desc->content.NM); @@ -1194,6 +1209,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_ELKHART_LAKE: if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; } else { @@ -1232,6 +1248,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_ELKHART_LAKE: mmio_le_writel(control, spibar + PCH100_REG_FDOC); return mmio_le_readl(spibar + PCH100_REG_FDOD); default: diff --git a/ichspi.c b/ichspi.c index 290deaa..76d853b 100644 --- a/ichspi.c +++ b/ichspi.c @@ -427,6 +427,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_ELKHART_LAKE: break; default: pprint_reg(HSFS, BERASE, reg_val, ", "); @@ -439,6 +440,7 @@ case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_ELKHART_LAKE: pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", "); pprint_reg(HSFS, WRSDIS, reg_val, ", "); break; @@ -1741,6 +1743,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_ELKHART_LAKE: num_pr = 6; /* Includes GPR0 */ reg_pr0 = PCH100_REG_FPR0; swseq_data.reg_ssfsc = PCH100_REG_SSFSC; @@ -1768,6 +1771,7 @@ num_freg = 10; break; case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_ELKHART_LAKE: num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */ break; case CHIPSET_300_SERIES_CANNON_POINT: @@ -1873,6 +1877,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_ELKHART_LAKE: tmp = mmio_readl(spibar + PCH100_REG_DLOCK); msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp); prettyprint_pch100_reg_dlock(tmp); @@ -1897,7 +1902,6 @@ "most likely\ndue to an active ME. Please see " "https://flashrom.org/ME for details.\n"); } - /* Handle PR registers */ for (i = 0; i < num_pr; i++) { /* if not locked down try to disable PR locks first */ @@ -1951,6 +1955,7 @@ case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_BAYTRAIL: + case CHIPSET_ELKHART_LAKE: break; default: ichspi_bbar = mmio_readl(spibar + ICH9_REG_BBAR); @@ -1985,6 +1990,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_ELKHART_LAKE: break; default: tmp = mmio_readl(spibar + ICH9_REG_FPB); @@ -2017,7 +2023,8 @@ (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT || ich_gen == CHIPSET_300_SERIES_CANNON_POINT || ich_gen == CHIPSET_400_SERIES_COMET_POINT || - ich_gen == CHIPSET_500_SERIES_TIGER_POINT)) { + ich_gen == CHIPSET_500_SERIES_TIGER_POINT || + ich_gen == CHIPSET_ELKHART_LAKE)) { msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n"); ich_spi_mode = ich_hwseq; } diff --git a/programmer.h b/programmer.h index b4f04e7..530706a 100644 --- a/programmer.h +++ b/programmer.h @@ -362,6 +362,7 @@ CHIPSET_500_SERIES_TIGER_POINT, CHIPSET_APOLLO_LAKE, CHIPSET_GEMINI_LAKE, + CHIPSET_ELKHART_LAKE, }; /* ichspi.c */ diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index a1e353b..f743510 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -238,6 +238,8 @@ cs = CHIPSET_APOLLO_LAKE; else if (strcmp(csn, "gemini") == 0) cs = CHIPSET_GEMINI_LAKE; + else if (strcmp(csn, "elkhart") == 0) + cs = CHIPSET_ELKHART_LAKE; } ret = read_ich_descriptors_from_dump(buf, len, &cs, &desc); -- To view, visit https://review.coreboot.org/c/flashrom/+/60711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I711e39a3ec9cd7098389231eaa1cb864d615a475 Gerrit-Change-Number: 60711 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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flashrom-gerrit January 2022