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Change subject: Makefile: Make pkg-config mandatory to find libpci
......................................................................
Patch Set 19: Code-Review+2
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/60325 )
Change subject: Makefile: replace RAW_ACCESS with RAW_MEM_ACCESS X86_MSR X86_PORT_IO
......................................................................
Patch Set 4: Code-Review+1
(4 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/60325/comment/3a8ab7c2_fdb17cbb
PS4, Line 10: realy
*really*
https://review.coreboot.org/c/flashrom/+/60325/comment/2e159dd8_40dbc976
PS4, Line 11: has handels
*handles*
File Makefile:
https://review.coreboot.org/c/flashrom/+/60325/comment/f309dfeb_b65eccd5
PS4, Line 835: -D'NEED_RAW_ACCESS=1'
If this vanishes, we should update `meson.build` as well.
https://review.coreboot.org/c/flashrom/+/60325/comment/1d0ef02d_9a16c1fd
PS4, Line 397: hwaccess.o
Is there anything left in it that isn't only needed in case of RAW_MEM_ACCESS?
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Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/60996 )
Change subject: linux_mtd: check ioctl() return value properly
......................................................................
linux_mtd: check ioctl() return value properly
Make the linux_mtd driver treat any negative return value from the
MEMERASE ioctl as an error. Previously it only treated -1 as an error.
BUG=b:213561594,b:210973586,b:182223106
BRANCH=none
TEST=builds
Change-Id: I40cfbdee2ab608fbe6c17d9cac6ec53ff224d9a4
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60996
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
---
M linux_mtd.c
1 file changed, 5 insertions(+), 3 deletions(-)
Approvals:
build bot (Jenkins): Verified
Angel Pons: Looks good to me, approved
Edward O'Callaghan: Looks good to me, approved
diff --git a/linux_mtd.c b/linux_mtd.c
index 04eccde..9d80a51 100644
--- a/linux_mtd.c
+++ b/linux_mtd.c
@@ -286,9 +286,11 @@
.length = data->erasesize,
};
- if (ioctl(fileno(data->dev_fp), MEMERASE, &erase_info) == -1) {
- msg_perr("%s: ioctl: %s\n", __func__, strerror(errno));
- return 1;
+ int ret = ioctl(fileno(data->dev_fp), MEMERASE, &erase_info);
+ if (ret < 0) {
+ msg_perr("%s: MEMERASE ioctl call returned %d, error: %s\n",
+ __func__, ret, strerror(errno));
+ return 1;
}
}
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Hello build bot (Jenkins), Nico Huber, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/59709
to look at the new patch set (#17).
Change subject: [RFC][OTP] spi25_statusreg: support reading/writing security register
......................................................................
[RFC][OTP] spi25_statusreg: support reading/writing security register
Not to be confused with "secure registers" of OTP.
Security register is a dedicated status register for security-related
bits. You don't write its value directly, issuing corresponding write
command with no data just sets OTP bit to 1 automatically.
No WREN is necessary, but at least some datasheets indicate BUSY state
after write command.
Unlike cases where OTP bit is part of SR and can only be written while
in OTP mode, security register can only be written outside of the mode.
Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M flash.h
M spi.h
M spi25_statusreg.c
3 files changed, 55 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/09/59709/17
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Hello build bot (Jenkins), Nico Huber, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/59403
to look at the new patch set (#19).
Change subject: [RFC][OTP] libflashrom,otp: add OTP regions management API
......................................................................
[RFC][OTP] libflashrom,otp: add OTP regions management API
This implements both OTP mode and secure registers variants. Support for
chips that have security registers is added in later commits.
Change-Id: Idf222b20973bf99a4e65e0fa8e464232969fd7e1
Signed-off-by: Hatim Kanchwala <hatim at hatimak.me>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M Makefile
M libflashrom.h
M meson.build
A otp.c
M otp.h
M writeprotect.h
6 files changed, 529 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/03/59403/19
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I'd like you to reexamine a change. Please visit
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Change subject: spi25_statusreg.c: add SR3 read/write support
......................................................................
spi25_statusreg.c: add SR3 read/write support
Adds support for reading and writing the third status register, which
needs to be enabled per chip.
Extended WRSR doesn't cover SR3, so only one feature flag is added.
Change-Id: Id987c544c02da2b956e6ad2c525265cac8f15be1
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
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3 files changed, 21 insertions(+), 0 deletions(-)
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Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59528 )
Change subject: spi25_statusreg: inline spi_write_register_flag()
......................................................................
Patch Set 22:
(1 comment)
File spi25_statusreg.c:
https://review.coreboot.org/c/flashrom/+/59528/comment/897c59df_200c31c0
PS21, Line 110: /* WRSR performs a self-timed erase before the changes take effect.
: * This may take 50-85 ms in most cases, and some chips apparently
: * allow running RDSR only once. Therefore pick an initial delay of
: * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed.
: */
: int i = 0;
: programmer_delay(100 * 1000);
: while (spi_read_status_register(flash) & SPI_SR_WIP) {
: if (++i > 490) {
: msg_cerr("Error: WIP bit after WRSR never cleared\n");
: return TIMEOUT_ERROR;
: }
: programmer_delay(10 * 1000);
: }
: return 0;
> This undoes changes to the waiting loop recently made in CB:58475.
Done, thanks!
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/59529
to look at the new patch set (#23).
Change subject: spi25_statusreg: delete read_status_register()
......................................................................
spi25_statusreg: delete read_status_register()
BUG=b:195381327,b:153800563
TEST=builds
BRANCH=none
Change-Id: I146b4b5439872e66c5d33e156451a729d248c7da
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M chipdrivers.h
M it87spi.c
M s25f.c
M spi25.c
M spi25_statusreg.c
5 files changed, 144 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/29/59529/23
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