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Change subject: spi25_statusreg: make register read/write functions generic
......................................................................
Patch Set 19:
(4 comments)
File spi25_statusreg.c:
https://review.coreboot.org/c/flashrom/+/58475/comment/8e41c1f8_d7b6e6da
PS14, Line 51: int result = spi_send_multicommand(flash, cmds);
> I think you're referring to the fact that it declares a variable in the middle of the function? Ther […]
Ack
File spi25_statusreg.c:
https://review.coreboot.org/c/flashrom/+/58475/comment/00d231f3_77c17f09
PS15, Line 63: */
> Changed in latest patch set.
Well, it's one thing to avoid a kludge for new use cases but something
different to change behavior for existing use cases. Unless we want
to test a lot of 15+ years old chips, please keep the behavior for SR1.
I'd be ok to risk to break things, but that would have to be a commit
on its own, e.g. after this series, a patch that removes the kludge even
for SR1.
https://review.coreboot.org/c/flashrom/+/58475/comment/c06493a7_69fdab9d
PS15, Line 84: *
> Done
Doesn't look done.
I'm not sure but I guess checkpatch would see this. Please just try.
See [1] for Linus' reasoning and [2] for the style choices in coreboot
(which avoids C++ comments but should be compatible with the style used
here).
[1] https://lkml.org/lkml/2016/7/8/625
[2] https://doc.coreboot.org/contributing/coding_style.html#commentinghttps://review.coreboot.org/c/flashrom/+/58475/comment/74beeeae_e612a757
PS15, Line 89: }
> The next commit adds nested ifs for handling chips with different ways of writing the same register, […]
Are you saying one can't use an if inside switch/case? I've looked
ahead and I don't see any real problem.
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Change subject: pcidev: Avoid internal programmer relying on pacc global
......................................................................
Patch Set 4:
(1 comment)
File pcidev.c:
https://review.coreboot.org/c/flashrom/+/59275/comment/72d3158c_a727f9cc
PS4, Line 154: start
Doesn't it stall on the second invocation? i.e. should this be `start->next`?
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Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/60087 )
Change subject: dediprog: wait for spi bulk read xfers to finish
......................................................................
dediprog: wait for spi bulk read xfers to finish
dediprog_bulk_read_poll()'s finish argument allows it to be used in two
distinct cases: where dediprog_bulk_read_poll will be called as part of
a loop (finish=0) and where dediprog_bulk_read_poll should wait for all
outstanding transfers to finish (finish=1). In both cases,
dediprog_bulk_read_poll() calls libusb to process events with a 10
second timeout.
After dediprog_spi_bulk_read() has queued the last transfers, it calls
dediprog_bulk_read_poll() with finish=0 when it should be finish=1.
finish=0 just happens to work because frequently the transfers finish in
the 10 second timeout.
Signed-off-by: Rick Altherr <rick(a)oxidecomputer.com>
Change-Id: If7cb541742c8620358c8e04275d8316131b2d1ab
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60087
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
---
M dediprog.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
Angel Pons: Looks good to me, approved
diff --git a/dediprog.c b/dediprog.c
index 939673c..8a05a7c 100644
--- a/dediprog.c
+++ b/dediprog.c
@@ -526,7 +526,7 @@
goto err_free;
}
/* Wait for transfers to finish. */
- if (dediprog_bulk_read_poll(dp_data->usb_ctx, &status, 0))
+ if (dediprog_bulk_read_poll(dp_data->usb_ctx, &status, 1))
goto err_free;
/* Check if everything has been transmitted. */
if ((status.finished_idx < count) || status.error)
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Change subject: dediprog: wait for spi bulk read xfers to finish
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
> Looks sensible to me, but I don't have a dediprog to test.
It's actually a recent regression. Sneaked into a revision of CB:56414.
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Change subject: Add Elkhart Lake support
......................................................................
Patch Set 1: Code-Review+1
(10 comments)
Patchset:
PS1:
Nice! looks almost ready :)
File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/60711/comment/d7633cdc_5e8ad909
PS1, Line 709: boot_straps = boot_straps_pch500;
The EDS says `bbs == 1` would be "UFS". Not sure how that's connected.
Is it related to eSPI?
https://review.coreboot.org/c/flashrom/+/60711/comment/8aa841ba_97c9aebe
PS1, Line 995: dev
So AFAICS, this is already 1f.5. We could save us the dance to find it
(the PCH100 code assumes it is hidden), e.g. extract the code in
enable_flash_pch100_or_c620() that works on `spi_dev` into a function
that we call here directly.
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/60711/comment/acd5afa7_31fcb7bc
PS1, Line 538: IFWI
Intel likes to haunt us with this it seems. Now all the non-BIOS firmware is
back in the TXE/ME region, but they still call it IFWI. Maybe we should just
change this back to BIOS. After all, everybody is calling it the BIOS region.
https://review.coreboot.org/c/flashrom/+/60711/comment/07f104ed_507f4713
PS1, Line 1033: return CHIPSET_500_SERIES_TIGER_POINT;
If the SPI guide is correct and I followed it, we would end up on this path.
We can identify EHL by CSSO == 0x6c (please check that in your descriptor), i.e.
if (content->CSSL == 0x11) {
if (content->CSSO == 0x68)
return CHIPSET_500_SERIES_TIGER_POINT;
if (content->CSSO == 0x6c)
return CHIPSET_ELKHART_LAKE;
}
https://review.coreboot.org/c/flashrom/+/60711/comment/d8037f2d_edc231ea
PS1, Line 1055: case CHIPSET_GEMINI_LAKE:
EHL here?
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/60711/comment/1c70e168_d2c3a495
PS1, Line 452: pprint_reg(HSFS, FLOCKDN, reg_val, "\n");
Looks like there are several new SAF (slave-attached flash?) bits. We
must have missed that when adding APL already. Or actually, missed
the whole function :-(
I don't mind leaving them out as long as the printed bits are correct.
https://review.coreboot.org/c/flashrom/+/60711/comment/bb51cd48_b6871c2e
PS1, Line 464: case CHIPSET_500_SERIES_TIGER_POINT:
Looks like we missed APL/GLK here? EHL should go here too it seems.
https://review.coreboot.org/c/flashrom/+/60711/comment/1b8bf0b8_05ee0633
PS1, Line 1774: case CHIPSET_ELKHART_LAKE:
This is tricky, the additional regs are at 0xe0. So it actually has 16.
https://review.coreboot.org/c/flashrom/+/60711/comment/ccdc3fba_8b023875
PS1, Line 2027: ich_gen == CHIPSET_ELKHART_LAKE)) {
Hmmm, would fit better below. Or maybe just merge the two if's. The idea
was to have an accurate message, but becomes harder with every new chip.
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Change subject: Add support for Intel Emmitsburg PCH
......................................................................
Patch Set 3:
(1 comment)
File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/54965/comment/34d05a85_5f5e98f8
PS3, Line 2076: enable_flash_c620
> Looking at the EDS (606161, rev 1.3), it seems closer to 300 series.
> At least wrt. the FREG registers.
Will anybody look into it?
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Change subject: [RFC][WIP] Makefile: use directory for object files
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/61034/comment/e83d4084_6ddf2141
PS1, Line 11: Makefile in util/ich_descriptors_tool does this already.
So it hides the object files but the final binary is still in the
source dir? I'm not sure if that's a good role-model. Not sure how
common it is, but I'm much used to a `build/` dir for everything.
File Makefile:
https://review.coreboot.org/c/flashrom/+/61034/comment/7d515c12_9531c34a
PS1, Line 925: _create_OBJPATH
Doesn't this trigger a re-build of everything every time?
https://review.coreboot.org/c/flashrom/+/61034/comment/244e328b_96b92aa6
PS1, Line 1093: -include $(OBJPATH)/$(OBJS:.o=.d)
This needs `$(addprefix )`.
Or maybe just do it one time, e.g.
OBJS := $(addprefix $(OBJPATH)/,$(OBJS))
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Change subject: Makefile: rename FEATURE_CFLAGS to FEATURE_FLAGS
......................................................................
Patch Set 4: Code-Review+2
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Change subject: Makefile: merge compiler, hwlibs, features targets into config target
......................................................................
Patch Set 10: Code-Review+2
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Change subject: Makefile: reorder make targets
......................................................................
Patch Set 3: Code-Review+2
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