September 2021 - flashrom-gerrit

Change in flashrom[master]: flashrom.c: Add 64KiB write granularity
by Nico Huber (Code Review) 12 Sep '21

12 Sep '21

Attention is currently required from: Michał Żygowski, Angel Pons, Michael Niewöhner. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55713 ) Change subject: flashrom.c: Add 64KiB write granularity ...................................................................... Patch Set 6: Code-Review+1 (1 comment) Patchset: PS6: Looks good, just waiting for the rest of the patch train. -- To view, visit https://review.coreboot.org/c/flashrom/+/55713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I69801f581d0cb9b85f6596de7e1267ef9317673f Gerrit-Change-Number: 55713 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Sun, 12 Sep 2021 10:48:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: Add Tiger Lake U Premium support
by Nico Huber (Code Review) 12 Sep '21

12 Sep '21

Attention is currently required from: Michał Żygowski, Paul Menzel. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55578 ) Change subject: Add Tiger Lake U Premium support ...................................................................... Patch Set 10: Code-Review+1 (8 comments) Patchset: PS10: Thanks for the update and ping. I think this change didn't get the attention it deserves because it's sitting amidst an unrelated patch train with status "Merge Conflict". It looks almost ready, so I think it's best to rebase it on master directly. One small cosmetic issue (`lp` suffix) and I think adding `BUS_ESPI` is raising unnecessary questions right now, so I'd just put a `0` where used it ;) File chipset_enable.c: https://review.coreboot.org/c/flashrom/+/55578/comment/e1b425b6_c00f58d2 PS3, Line 659: { "eSPI", BUS_LPC | BUS_FWH } }; > Ping I still wonder if eSPI is a bus for flashes at all? See comments on the enum change. Probably easiest to just put a 0 here. The value is only processed by the calling function and there is nothing to be done for eSPI atm. File chipset_enable.c: https://review.coreboot.org/c/flashrom/+/55578/comment/a013a974_92bd3938 PS10, Line 657: _lp The `lp` suffix was previously used when there was a low-power version with different behavior. I don't think this is the case with TGP? File flash.h: https://review.coreboot.org/c/flashrom/+/55578/comment/dcee4975_fa188165 PS10, Line 70: BUS_ESPI = 1 << 5, Checking how all paths react to this change takes some time and should eventually be reviewed as a separate commit. I had a quick look and it seems BUS_NONSPI (see below) might be the only incon- sistency. I guess if you try to fix that some unit-test will break and fixing that might lead to the question if flashbuses_to_text() should be updated, etc... So I wonder if it's worth to add this before we actually act on the new value anywhere. Coming back to the question if there are flash chips for eSPI. https://review.coreboot.org/c/flashrom/+/55578/comment/cffd06c6_8268ae6d PS10, Line 71: BUS_NONSPI = BUS_PARALLEL | BUS_LPC | BUS_FWH, This would definitely need an update. Although, I'm not sure if it is consistently used throughout flashrom code. File ich_descriptors.c: https://review.coreboot.org/c/flashrom/+/55578/comment/d83477ee_84f6d4e3 PS5, Line 278: return "reserved"; > Kindly asking to check if it does look good now Ack Thanks for taking fully care of `freq_read`. https://review.coreboot.org/c/flashrom/+/55578/comment/eddd80d8_3cfef3a9 PS5, Line 967: return CHIPSET_500_SERIES_TIGER_POINT; > Please check Done File ich_descriptors.c: https://review.coreboot.org/c/flashrom/+/55578/comment/d0469aac_db77eedd PS10, Line 316: msg_pdbg2("Read Clock Frequency: %s\n", "reserved"); Nit, I think we can just skip printing anything here. -- To view, visit https://review.coreboot.org/c/flashrom/+/55578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd Gerrit-Change-Number: 55578 Gerrit-PatchSet: 10 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 12 Sep 2021 10:45:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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Change in flashrom[master]: ich_descriptors_tool: Add missing Comet Point in usage
by Nico Huber (Code Review) 12 Sep '21

12 Sep '21

Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/55993 ) Change subject: ich_descriptors_tool: Add missing Comet Point in usage ...................................................................... ich_descriptors_tool: Add missing Comet Point in usage Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ia1e3e231944513521d5db064340a0247f1884290 Reviewed-on: https://review.coreboot.org/c/flashrom/+/55993 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M util/ich_descriptors_tool/ich_descriptors_tool.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index bfeedc1..0807f5e 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -135,6 +135,7 @@ "\t- \"9\" or \"wildcat\" for Intel's 9 series chipsets.\n" "\t- \"100\" or \"sunrise\" for Intel's 100 series chipsets.\n" "\t- \"300\" or \"cannon\" for Intel's 300 series chipsets.\n" +"\t- \"400\" or \"comet\" for Intel's 400 series chipsets.\n" "If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n" "the GbE blob that is required to initialize the GbE are also dumped to files.\n", argv[0], argv[0]); 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/flashrom/+/55993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia1e3e231944513521d5db064340a0247f1884290 Gerrit-Change-Number: 55993 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: chipset_enable.c: Add Ids for recent Intel chipsets
by Selma Bensaid (Code Review) 10 Sep '21

10 Sep '21

Attention is currently required from: Bora Guvendik, Anil Kumar K. Selma Bensaid has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/57560 ) Change subject: chipset_enable.c: Add Ids for recent Intel chipsets ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/flashrom/+/57560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iff387076567e639485ac15c25c1bcc8c37a07037 Gerrit-Change-Number: 57560 Gerrit-PatchSet: 3 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Nikolai Artemiev <nartemiev(a)chromium.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Comment-Date: Fri, 10 Sep 2021 21:13:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: chipset_enable.c: Add Ids for recent Intel chipsets
by Anil Kumar K (Code Review) 10 Sep '21

10 Sep '21

Attention is currently required from: Bora Guvendik. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/57560 ) Change subject: chipset_enable.c: Add Ids for recent Intel chipsets ...................................................................... Patch Set 3: (2 comments) File chipset_enable.c: https://review.coreboot.org/c/flashrom/+/57560/comment/b2bdfffe_2ef06019 PS2, Line 2018: > can you align these please Ack https://review.coreboot.org/c/flashrom/+/57560/comment/f58c58ed_7cd580ea PS2, Line 2020: > can you align these please Ack -- To view, visit https://review.coreboot.org/c/flashrom/+/57560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iff387076567e639485ac15c25c1bcc8c37a07037 Gerrit-Change-Number: 57560 Gerrit-PatchSet: 3 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Nikolai Artemiev <nartemiev(a)chromium.org> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Comment-Date: Fri, 10 Sep 2021 17:58:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: comment

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Change in flashrom[master]: chipset_enable.c: Add Ids for recent Intel chipsets
by Bora Guvendik (Code Review) 10 Sep '21

10 Sep '21

Attention is currently required from: Anil Kumar K. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/57560 ) Change subject: chipset_enable.c: Add Ids for recent Intel chipsets ...................................................................... Patch Set 2: (2 comments) File chipset_enable.c: https://review.coreboot.org/c/flashrom/+/57560/comment/8c449314_3269ab32 PS2, Line 2018: can you align these please https://review.coreboot.org/c/flashrom/+/57560/comment/373765c1_f0b03083 PS2, Line 2020: can you align these please -- To view, visit https://review.coreboot.org/c/flashrom/+/57560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iff387076567e639485ac15c25c1bcc8c37a07037 Gerrit-Change-Number: 57560 Gerrit-PatchSet: 2 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Nikolai Artemiev <nartemiev(a)chromium.org> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Comment-Date: Fri, 10 Sep 2021 17:45:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: chipset_enable.c: Add Ids for recent Intel chipsets
by Anil Kumar K (Code Review) 10 Sep '21

10 Sep '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/57560 to look at the new patch set (#2). Change subject: chipset_enable.c: Add Ids for recent Intel chipsets ...................................................................... chipset_enable.c: Add Ids for recent Intel chipsets - Skylake, Lewisburg, Geminilake, Cannonlake, Icelake, Jasperlake, Tigerlake and Alderlake BRANCH=none TEST= flashrom --programmer internal --flash-name on ADL-M RVP, returns "Found chipset "Intel Alderlake-P / M" Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: Iff387076567e639485ac15c25c1bcc8c37a07037 --- M chipset_enable.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/60/57560/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/57560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iff387076567e639485ac15c25c1bcc8c37a07037 Gerrit-Change-Number: 57560 Gerrit-PatchSet: 2 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: chipset_enable.c: Add Ids for recent Intel chipsets
by Anil Kumar K (Code Review) 10 Sep '21

10 Sep '21

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/57560 ) Change subject: chipset_enable.c: Add Ids for recent Intel chipsets ...................................................................... chipset_enable.c: Add Ids for recent Intel chipsets - Skylake, Lewisburg, Geminilake, Cannonlake, Icelake, Jasperlake, Tigerlake and Alderlake Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: Iff387076567e639485ac15c25c1bcc8c37a07037 --- M chipset_enable.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/60/57560/1 diff --git a/chipset_enable.c b/chipset_enable.c index 110d7a9..b8465ad 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2015,6 +2015,15 @@ {0x8086, 0x9cc7, B_FS, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp}, {0x8086, 0x9cc9, B_FS, NT, "Intel", "Broadwell Y Base", enable_flash_pch9_lp}, {0x8086, 0x9ccb, B_FS, NT, "Intel", "Broadwell H", enable_flash_pch9}, + {0x8086, 0x9d24, B_FS, OK, "Intel", "Skylake", enable_flash_pch100}, + {0x8086, 0xa224, B_FS, OK, "Intel", "Lewisburg", enable_flash_pch100}, + {0x8086, 0x31f0, B_FS, OK, "Intel", "Geminilake", enable_flash_apl}, + {0x8086, 0x9da4, B_FS, OK, "Intel", "Cannonlake", enable_flash_pch100}, + {0x8086, 0x34a4, B_FS, OK, "Intel", "Icelake", enable_flash_pch100}, + {0x8086, 0x4da4, B_FS, OK, "Intel", "Jasperlake", enable_flash_pch100}, + {0x8086, 0xa0a4, B_FS, OK, "Intel", "Tigerlake", enable_flash_pch100}, + {0x8086, 0x7aa4, B_FS, OK, "Intel", "Alderlake-S", enable_flash_pch100}, + {0x8086, 0x51a4, B_FS, OK, "Intel", "Alderlake-P / M", enable_flash_pch100}, {0x8086, 0x9d41, B_S, NT, "Intel", "Skylake / Kaby Lake Sample", enable_flash_pch100}, {0x8086, 0x9d43, B_S, NT, "Intel", "Skylake U Base", enable_flash_pch100}, {0x8086, 0x9d46, B_S, NT, "Intel", "Skylake Y Premium", enable_flash_pch100}, -- To view, visit https://review.coreboot.org/c/flashrom/+/57560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iff387076567e639485ac15c25c1bcc8c37a07037 Gerrit-Change-Number: 57560 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: chipset_enable.c: Add TGP-H IDs
by Tim Crawford (Code Review) 10 Sep '21

10 Sep '21

Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/57533 ) Change subject: chipset_enable.c: Add TGP-H IDs ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/flashrom/+/57533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I96f63253d42578151f99dcbb42347afecc03f49d Gerrit-Change-Number: 57533 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 10 Sep 2021 14:37:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: Add support for Intel Emmitsburg PCH
by David Hendricks (Code Review) 10 Sep '21

10 Sep '21

Attention is currently required from: Jonathan Zhang. David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54965 ) Change subject: Add support for Intel Emmitsburg PCH ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > Did anybody look into it? Yes, and IMO we should find a better heuristic or require the user to specify a ICH/PCH generation or PCI ID when the programmer is not "internal". ICCRIBA is obsolete and is reserved on chipsets for the past several years (6-series was the newest chipset with it AFAICT), so checking `if (content->ICCRIBA == 0x00)` works by accident in most cases it seems. The ISL/PSL field shows inconsistent results between what's documented and what's in BKC images. Ibex Peak (5-series?) seems obsolete. I can't even find a SPI programming guide for it, though maybe you have a document number handy? -- To view, visit https://review.coreboot.org/c/flashrom/+/54965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2a1bb7467e693d1583aa885fa0e277075edd4a3e Gerrit-Change-Number: 54965 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Deomid "rojer" Ryabkov <rojer9(a)fb.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Comment-Date: Fri, 10 Sep 2021 06:23:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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flashrom-gerrit September 2021