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Change subject: dediprog.c: Drop dediprog_ prefix for spi data struct members
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
File dediprog.c:
https://review.coreboot.org/c/flashrom/+/56415/comment/101a9f51_e5272551
PS4, Line 1058:
Looks like one tab too much now, maybe it would even look better w/o
a line break or with an earlier one.
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Change subject: dediprog.c: Refactor singleton states into reentrant pattern
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
File dediprog.c:
https://review.coreboot.org/c/flashrom/+/56414/comment/5610a75d_898c9e2e
PS3, Line 221: const int finish,
> I used "at least after the opening parenthesis" option. […]
I don't think there is a written rule. There are three common ways
to indent parameter lists, I think, by decreasing popularity (by my
own perception):
/* Aligned right after the opening parenthesis */
void some_function(int some_param,
int another_param)
/* All aligned to two tabs */
void function_with_a_long_name_that_leaves_little_space(
int some_param,
int another_param)
/* Aligned after the opening parenthesis, with tabs only */
void some_function(int some_param,
int another_param)
I'd say for review, it just shouldn't look obviously wrong. To me,
dediprog_read() still does.
If I had to extract a rule from the most common practice it would
be this: All parameter declarations should be aligned to the
same column, but never with the function body (hence the two
tabs in the second example and not just one). That would apply
to the first two examples above.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/57437 )
Change subject: tests: Make chip definitions static global
......................................................................
Patch Set 3:
(6 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/57437/comment/a07f7a08_8db02933
PS3, Line 7: tests: Make chip definitions static global
The summary line should somehow cover all the changes. If you
do much in a single commit, it might simply end up as a vague
"tests: Revise chip definitions".
https://review.coreboot.org/c/flashrom/+/57437/comment/f839994d_210c4d9d
PS3, Line 13: was confusing. Mock chip looks more realistic now.
Generally, moving and changing code in a single commit often
makes the review unnecessarily harder. Not too bad in this case.
File tests/chip.c:
https://review.coreboot.org/c/flashrom/+/57437/comment/c4df88a7_c453873f
PS3, Line 24: CHIP_TOTAL_SIZE
There's another chip below with a different size. Should we name it
`MOCKED_CHIP_SIZE` maybe?
https://review.coreboot.org/c/flashrom/+/57437/comment/e3e24329_c22654e1
PS3, Line 24: #define CHIP_TOTAL_SIZE 8388608
Please make use of the KiB/MiB macros. This should be `(8*MiB)` (usually
written without spaces around the asterisk).
https://review.coreboot.org/c/flashrom/+/57437/comment/d733ef15_1b8a06fa
PS3, Line 128: static struct flashchip chip_8MiB = {
Should we make them `const` and then work on a copy on the stack?
That way we'd have a fresh copy for every test.
https://review.coreboot.org/c/flashrom/+/57437/comment/70b14686_488e1b5a
PS3, Line 130: .total_size = 8 * 1024,
CHIP_TOTAL_SIZE / KiB
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/57326 )
Change subject: tests: Add tests to read from chip
......................................................................
Patch Set 3: Code-Review+1
(3 comments)
File tests/chip.c:
https://review.coreboot.org/c/flashrom/+/57326/comment/198dbcb9_4301177b
PS1, Line 246: };
> Yes right, they started to repeat once more tests have been added. I created CB:57437 for this.
Thanks. Often it's better to clean up first, though. Doesn't matter for this
chain anymore ;) My rule of thumb: if you have to touch many lines again later
in the chain, the order is probably wrong.
File tests/tests.c:
https://review.coreboot.org/c/flashrom/+/57326/comment/53985f31_e98f9d1f
PS3, Line 185: len
This is `nmemb` (according to manpage). `len` is easy to confuse with
a length in bytes.
https://review.coreboot.org/c/flashrom/+/57326/comment/3c8d2e0e_cfa0d517
PS3, Line 188: size * len
This should return just `len` (actually `nmemb`). It only works because
flashrom passes 1 as `size`.
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Change subject: tests: Extract setup and teardown for chip tests
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File tests/chip.c:
https://review.coreboot.org/c/flashrom/+/57436/comment/de80f98a_0fc8f33c
PS1, Line 29: g_chip_state
> Good idea, totally makes sense! I was going to do it quickly, but then I realised I don't know how t […]
Alas, there is no proper abstraction yet. Some of the field of struct
flashrom_flashctx look chip specific (e.g. those about SPI 4BA), so
looks like there is a reason for another data pointer even without
the tests.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/56023 )
Change subject: board_enable.c: Add ME unlock function for TUXEDO laptops
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS7:
> Some feedback about the current state of the code vs open discussions would be appreciated. […]
I'm still confused why this is done deep in flashrom on the programmer path
and not in a separate binary (which could share any code necessary ofc). If
you could provide some details on the overall workflow, that could get the
discussion started I guess.
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Change subject: acpi_ec: Implement basic ACPI embedded controller API
......................................................................
Patch Set 8:
(2 comments)
File acpi_ec.h:
https://review.coreboot.org/c/flashrom/+/55714/comment/5cbc35a9_b182327e
PS4, Line 41: bool ec_wait_for_ibuf(uint8_t control_port, unsigned int max_checks);
: bool ec_wait_for_obuf(uint8_t control_port, unsigned int max_checks);
> Done
Still there.
File acpi_ec.h:
https://review.coreboot.org/c/flashrom/+/55714/comment/867b2d82_c7ca7902
PS1, Line 41: bool ec_wait_for_ibuf(uint8_t control_port);
: bool ec_wait_for_obuf(uint8_t control_port, unsigned int max_checks);
> The erase command required longer timeout on output buffer flag. […]
So, I've been looking through the code of the follow ups. There is indeed
only this one case where a non-default value is passed. That you need a
higher timeout there is clear. But why do you need a lower one for every-
thing else?
The calls would look much cleaner without this parameter, or at least by
making use of the default by passing 0. And we wouldn't have to expose
EC_MAX_STATUS_CHECKS in any case.
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Change subject: Add Tiger Lake U Premium support
......................................................................
Patch Set 10: Code-Review+1
(8 comments)
Patchset:
PS10:
Thanks for the update and ping. I think this change didn't get
the attention it deserves because it's sitting amidst an unrelated
patch train with status "Merge Conflict".
It looks almost ready, so I think it's best to rebase it on master
directly. One small cosmetic issue (`lp` suffix) and I think adding
`BUS_ESPI` is raising unnecessary questions right now, so I'd just
put a `0` where used it ;)
File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/55578/comment/e1b425b6_c00f58d2
PS3, Line 659: { "eSPI", BUS_LPC | BUS_FWH } };
> Ping
I still wonder if eSPI is a bus for flashes at all? See
comments on the enum change.
Probably easiest to just put a 0 here. The value is only processed by
the calling function and there is nothing to be done for eSPI atm.
File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/55578/comment/a013a974_92bd3938
PS10, Line 657: _lp
The `lp` suffix was previously used when there was a low-power version
with different behavior. I don't think this is the case with TGP?
File flash.h:
https://review.coreboot.org/c/flashrom/+/55578/comment/dcee4975_fa188165
PS10, Line 70: BUS_ESPI = 1 << 5,
Checking how all paths react to this change takes some time and
should eventually be reviewed as a separate commit. I had a quick
look and it seems BUS_NONSPI (see below) might be the only incon-
sistency. I guess if you try to fix that some unit-test will break
and fixing that might lead to the question if flashbuses_to_text()
should be updated, etc...
So I wonder if it's worth to add this before we actually act on
the new value anywhere. Coming back to the question if there are
flash chips for eSPI.
https://review.coreboot.org/c/flashrom/+/55578/comment/cffd06c6_8268ae6d
PS10, Line 71: BUS_NONSPI = BUS_PARALLEL | BUS_LPC | BUS_FWH,
This would definitely need an update. Although, I'm not sure if it is
consistently used throughout flashrom code.
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/55578/comment/d83477ee_84f6d4e3
PS5, Line 278: return "reserved";
> Kindly asking to check if it does look good now
Ack
Thanks for taking fully care of `freq_read`.
https://review.coreboot.org/c/flashrom/+/55578/comment/eddd80d8_3cfef3a9
PS5, Line 967: return CHIPSET_500_SERIES_TIGER_POINT;
> Please check
Done
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/55578/comment/d0469aac_db77eedd
PS10, Line 316: msg_pdbg2("Read Clock Frequency: %s\n", "reserved");
Nit, I think we can just skip printing anything here.
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Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/55993 )
Change subject: ich_descriptors_tool: Add missing Comet Point in usage
......................................................................
ich_descriptors_tool: Add missing Comet Point in usage
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: Ia1e3e231944513521d5db064340a0247f1884290
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55993
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
---
M util/ich_descriptors_tool/ich_descriptors_tool.c
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c
index bfeedc1..0807f5e 100644
--- a/util/ich_descriptors_tool/ich_descriptors_tool.c
+++ b/util/ich_descriptors_tool/ich_descriptors_tool.c
@@ -135,6 +135,7 @@
"\t- \"9\" or \"wildcat\" for Intel's 9 series chipsets.\n"
"\t- \"100\" or \"sunrise\" for Intel's 100 series chipsets.\n"
"\t- \"300\" or \"cannon\" for Intel's 300 series chipsets.\n"
+"\t- \"400\" or \"comet\" for Intel's 400 series chipsets.\n"
"If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n"
"the GbE blob that is required to initialize the GbE are also dumped to files.\n",
argv[0], argv[0]);
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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