October 2021 - flashrom-gerrit

Change in flashrom[master]: ichspi: Split very long init function into two
by Anastasia Klimchuk (Code Review) 29 Oct '21

29 Oct '21

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/58735 ) Change subject: ichspi: Split very long init function into two ...................................................................... ichspi: Split very long init function into two ich_init_spi is very long, but logically it can be split. Init function detects the chipset and then the rest of operations depends on the chipset. Init function is more readable now, it consists of only a switch. TEST ME ON DEVICE BUG=b:204488958 Change-Id: I6789bc456a4878e6555831ae0b80ecbdbf62938b Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M ichspi.c 1 file changed, 268 insertions(+), 252 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/35/58735/1 diff --git a/ichspi.c b/ichspi.c index d345af2..9db241c 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1710,7 +1710,46 @@ .erase = ich_hwseq_block_erase, }; -int ich_init_spi(void *spibar, enum ich_chipset ich_gen) +static int init_ich7_spi(void *spibar, enum ich_chipset ich_gen) +{ + unsigned int i; + + msg_pdbg("0x00: 0x%04x (SPIS)\n", + mmio_readw(spibar + 0)); + msg_pdbg("0x02: 0x%04x (SPIC)\n", + mmio_readw(spibar + 2)); + msg_pdbg("0x04: 0x%08x (SPIA)\n", + mmio_readl(spibar + 4)); + ichspi_bbar = mmio_readl(spibar + 0x50); + msg_pdbg("0x50: 0x%08x (BBAR)\n", + ichspi_bbar); + msg_pdbg("0x54: 0x%04x (PREOP)\n", + mmio_readw(spibar + 0x54)); + msg_pdbg("0x56: 0x%04x (OPTYPE)\n", + mmio_readw(spibar + 0x56)); + msg_pdbg("0x58: 0x%08x (OPMENU)\n", + mmio_readl(spibar + 0x58)); + msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", + mmio_readl(spibar + 0x5c)); + + for (i = 0; i < 3; i++) { + int offs; + offs = 0x60 + (i * 4); + msg_pdbg("0x%02x: 0x%08x (PBR%u)\n", offs, + mmio_readl(spibar + offs), i); + } + if (mmio_readw(spibar) & (1 << 15)) { + msg_pwarn("WARNING: SPI Configuration Lockdown activated.\n"); + ichspi_lock = 1; + } + ich_init_opcodes(ich_gen); + ich_set_bbar(0, ich_gen); + register_spi_master(&spi_master_ich7, NULL); + + return 0; +} + +static int init_ich_default(void *spibar, enum ich_chipset ich_gen) { unsigned int i; uint16_t tmp2; @@ -1724,6 +1763,7 @@ ich_hwseq, ich_swseq } ich_spi_mode = ich_auto; + size_t num_freg, num_pr, reg_pr0; ich_generation = ich_gen; @@ -1777,276 +1817,252 @@ break; } - switch (ich_gen) { - case CHIPSET_ICH7: - case CHIPSET_TUNNEL_CREEK: - case CHIPSET_CENTERTON: - msg_pdbg("0x00: 0x%04x (SPIS)\n", - mmio_readw(spibar + 0)); - msg_pdbg("0x02: 0x%04x (SPIC)\n", - mmio_readw(spibar + 2)); - msg_pdbg("0x04: 0x%08x (SPIA)\n", - mmio_readl(spibar + 4)); - ichspi_bbar = mmio_readl(spibar + 0x50); - msg_pdbg("0x50: 0x%08x (BBAR)\n", - ichspi_bbar); - msg_pdbg("0x54: 0x%04x (PREOP)\n", - mmio_readw(spibar + 0x54)); - msg_pdbg("0x56: 0x%04x (OPTYPE)\n", - mmio_readw(spibar + 0x56)); - msg_pdbg("0x58: 0x%08x (OPMENU)\n", - mmio_readl(spibar + 0x58)); - msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", - mmio_readl(spibar + 0x5c)); - for (i = 0; i < 3; i++) { - int offs; - offs = 0x60 + (i * 4); - msg_pdbg("0x%02x: 0x%08x (PBR%u)\n", offs, - mmio_readl(spibar + offs), i); - } - if (mmio_readw(spibar) & (1 << 15)) { - msg_pwarn("WARNING: SPI Configuration Lockdown activated.\n"); - ichspi_lock = 1; - } - ich_init_opcodes(ich_gen); - ich_set_bbar(0, ich_gen); - register_spi_master(&spi_master_ich7, NULL); - break; - case CHIPSET_ICH8: - default: /* Future version might behave the same */ - arg = extract_programmer_param("ich_spi_mode"); - if (arg && !strcmp(arg, "hwseq")) { - ich_spi_mode = ich_hwseq; - msg_pspew("user selected hwseq\n"); - } else if (arg && !strcmp(arg, "swseq")) { - ich_spi_mode = ich_swseq; - msg_pspew("user selected swseq\n"); - } else if (arg && !strcmp(arg, "auto")) { - msg_pspew("user selected auto\n"); - ich_spi_mode = ich_auto; - } else if (arg && !strlen(arg)) { - msg_perr("Missing argument for ich_spi_mode.\n"); - free(arg); - return ERROR_FATAL; - } else if (arg) { - msg_perr("Unknown argument for ich_spi_mode: %s\n", - arg); - free(arg); - return ERROR_FATAL; - } + arg = extract_programmer_param("ich_spi_mode"); + if (arg && !strcmp(arg, "hwseq")) { + ich_spi_mode = ich_hwseq; + msg_pspew("user selected hwseq\n"); + } else if (arg && !strcmp(arg, "swseq")) { + ich_spi_mode = ich_swseq; + msg_pspew("user selected swseq\n"); + } else if (arg && !strcmp(arg, "auto")) { + msg_pspew("user selected auto\n"); + ich_spi_mode = ich_auto; + } else if (arg && !strlen(arg)) { + msg_perr("Missing argument for ich_spi_mode.\n"); free(arg); + return ERROR_FATAL; + } else if (arg) { + msg_perr("Unknown argument for ich_spi_mode: %s\n", + arg); + free(arg); + return ERROR_FATAL; + } + free(arg); - tmp2 = mmio_readw(spibar + ICH9_REG_HSFS); - msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); - prettyprint_ich9_reg_hsfs(tmp2, ich_gen); - if (tmp2 & HSFS_FLOCKDN) { - msg_pinfo("SPI Configuration is locked down.\n"); - ichspi_lock = 1; - } - if (tmp2 & HSFS_FDV) - desc_valid = 1; - if (!(tmp2 & HSFS_FDOPSS) && desc_valid) - msg_pinfo("The Flash Descriptor Override Strap-Pin is set. Restrictions implied by\n" - "the Master Section of the flash descriptor are NOT in effect. Please note\n" - "that Protected Range (PR) restrictions still apply.\n"); - ich_init_opcodes(ich_gen); + tmp2 = mmio_readw(spibar + ICH9_REG_HSFS); + msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); + prettyprint_ich9_reg_hsfs(tmp2, ich_gen); + if (tmp2 & HSFS_FLOCKDN) { + msg_pinfo("SPI Configuration is locked down.\n"); + ichspi_lock = 1; + } + if (tmp2 & HSFS_FDV) + desc_valid = 1; + if (!(tmp2 & HSFS_FDOPSS) && desc_valid) + msg_pinfo("The Flash Descriptor Override Strap-Pin is set. Restrictions implied by\n" + "the Master Section of the flash descriptor are NOT in effect. Please note\n" + "that Protected Range (PR) restrictions still apply.\n"); + ich_init_opcodes(ich_gen); - if (desc_valid) { - tmp2 = mmio_readw(spibar + ICH9_REG_HSFC); - msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); - prettyprint_ich9_reg_hsfc(tmp2, ich_gen); - } + if (desc_valid) { + tmp2 = mmio_readw(spibar + ICH9_REG_HSFC); + msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); + prettyprint_ich9_reg_hsfc(tmp2, ich_gen); + } - tmp = mmio_readl(spibar + ICH9_REG_FADDR); - msg_pdbg2("0x08: 0x%08x (FADDR)\n", tmp); + tmp = mmio_readl(spibar + ICH9_REG_FADDR); + msg_pdbg2("0x08: 0x%08x (FADDR)\n", tmp); + switch (ich_gen) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: + case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: + tmp = mmio_readl(spibar + PCH100_REG_DLOCK); + msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp); + prettyprint_pch100_reg_dlock(tmp); + break; + default: + break; + } + + if (desc_valid) { + tmp = mmio_readl(spibar + ICH9_REG_FRAP); + msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); + msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); + msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); + msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); + msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); + + /* Handle FREGx and FRAP registers */ + for (i = 0; i < num_freg; i++) + ich_spi_rw_restricted |= ich9_handle_frap(tmp, i); + if (ich_spi_rw_restricted) + msg_pinfo("Not all flash regions are freely accessible by flashrom. This is " + "most likely\ndue to an active ME. Please see " + "https://flashrom.org/ME for details.\n"); + } + + /* Handle PR registers */ + for (i = 0; i < num_pr; i++) { + /* if not locked down try to disable PR locks first */ + if (!ichspi_lock) + ich9_set_pr(reg_pr0, i, 0, 0); + ich_spi_rw_restricted |= ich9_handle_pr(reg_pr0, i); + } + + switch (ich_spi_rw_restricted) { + case WRITE_PROT: + msg_pwarn("At least some flash regions are write protected. For write operations,\n" + "you should use a flash layout and include only writable regions. See\n" + "manpage for more details.\n"); + break; + case READ_PROT: + case LOCKED: + msg_pwarn("At least some flash regions are read protected. You have to use a flash\n" + "layout and include only accessible regions. For write operations, you'll\n" + "additionally need the --noverify-all switch. See manpage for more details.\n" + ); + break; + } + + tmp = mmio_readl(spibar + swseq_data.reg_ssfsc); + msg_pdbg("0x%zx: 0x%02x (SSFS)\n", swseq_data.reg_ssfsc, tmp & 0xff); + prettyprint_ich9_reg_ssfs(tmp); + if (tmp & SSFS_FCERR) { + msg_pdbg("Clearing SSFS.FCERR\n"); + mmio_writeb(SSFS_FCERR, spibar + swseq_data.reg_ssfsc); + } + msg_pdbg("0x%zx: 0x%06x (SSFC)\n", swseq_data.reg_ssfsc + 1, tmp >> 8); + prettyprint_ich9_reg_ssfc(tmp); + + msg_pdbg("0x%zx: 0x%04x (PREOP)\n", + swseq_data.reg_preop, mmio_readw(spibar + swseq_data.reg_preop)); + msg_pdbg("0x%zx: 0x%04x (OPTYPE)\n", + swseq_data.reg_optype, mmio_readw(spibar + swseq_data.reg_optype)); + msg_pdbg("0x%zx: 0x%08x (OPMENU)\n", + swseq_data.reg_opmenu, mmio_readl(spibar + swseq_data.reg_opmenu)); + msg_pdbg("0x%zx: 0x%08x (OPMENU+4)\n", + swseq_data.reg_opmenu + 4, mmio_readl(spibar + swseq_data.reg_opmenu + 4)); + + if (desc_valid) { switch (ich_gen) { + case CHIPSET_ICH8: case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: - tmp = mmio_readl(spibar + PCH100_REG_DLOCK); - msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp); - prettyprint_pch100_reg_dlock(tmp); + case CHIPSET_BAYTRAIL: break; default: + ichspi_bbar = mmio_readl(spibar + ICH9_REG_BBAR); + msg_pdbg("0x%x: 0x%08x (BBAR)\n", ICH9_REG_BBAR, ichspi_bbar); + ich_set_bbar(0, ich_gen); break; } - if (desc_valid) { - tmp = mmio_readl(spibar + ICH9_REG_FRAP); - msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); - msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); - msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); - msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); - msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); - - /* Handle FREGx and FRAP registers */ - for (i = 0; i < num_freg; i++) - ich_spi_rw_restricted |= ich9_handle_frap(tmp, i); - if (ich_spi_rw_restricted) - msg_pinfo("Not all flash regions are freely accessible by flashrom. This is " - "most likely\ndue to an active ME. Please see " - "https://flashrom.org/ME for details.\n"); - } - - /* Handle PR registers */ - for (i = 0; i < num_pr; i++) { - /* if not locked down try to disable PR locks first */ - if (!ichspi_lock) - ich9_set_pr(reg_pr0, i, 0, 0); - ich_spi_rw_restricted |= ich9_handle_pr(reg_pr0, i); - } - - switch (ich_spi_rw_restricted) { - case WRITE_PROT: - msg_pwarn("At least some flash regions are write protected. For write operations,\n" - "you should use a flash layout and include only writable regions. See\n" - "manpage for more details.\n"); - break; - case READ_PROT: - case LOCKED: - msg_pwarn("At least some flash regions are read protected. You have to use a flash\n" - "layout and include only accessible regions. For write operations, you'll\n" - "additionally need the --noverify-all switch. See manpage for more details.\n" - ); - break; - } - - tmp = mmio_readl(spibar + swseq_data.reg_ssfsc); - msg_pdbg("0x%zx: 0x%02x (SSFS)\n", swseq_data.reg_ssfsc, tmp & 0xff); - prettyprint_ich9_reg_ssfs(tmp); - if (tmp & SSFS_FCERR) { - msg_pdbg("Clearing SSFS.FCERR\n"); - mmio_writeb(SSFS_FCERR, spibar + swseq_data.reg_ssfsc); - } - msg_pdbg("0x%zx: 0x%06x (SSFC)\n", swseq_data.reg_ssfsc + 1, tmp >> 8); - prettyprint_ich9_reg_ssfc(tmp); - - msg_pdbg("0x%zx: 0x%04x (PREOP)\n", - swseq_data.reg_preop, mmio_readw(spibar + swseq_data.reg_preop)); - msg_pdbg("0x%zx: 0x%04x (OPTYPE)\n", - swseq_data.reg_optype, mmio_readw(spibar + swseq_data.reg_optype)); - msg_pdbg("0x%zx: 0x%08x (OPMENU)\n", - swseq_data.reg_opmenu, mmio_readl(spibar + swseq_data.reg_opmenu)); - msg_pdbg("0x%zx: 0x%08x (OPMENU+4)\n", - swseq_data.reg_opmenu + 4, mmio_readl(spibar + swseq_data.reg_opmenu + 4)); - - if (desc_valid) { - switch (ich_gen) { - case CHIPSET_ICH8: - case CHIPSET_100_SERIES_SUNRISE_POINT: - case CHIPSET_C620_SERIES_LEWISBURG: - case CHIPSET_300_SERIES_CANNON_POINT: - case CHIPSET_400_SERIES_COMET_POINT: - case CHIPSET_APOLLO_LAKE: - case CHIPSET_GEMINI_LAKE: - case CHIPSET_BAYTRAIL: - break; - default: - ichspi_bbar = mmio_readl(spibar + ICH9_REG_BBAR); - msg_pdbg("0x%x: 0x%08x (BBAR)\n", ICH9_REG_BBAR, ichspi_bbar); - ich_set_bbar(0, ich_gen); - break; - } - - if (ich_gen == CHIPSET_ICH8) { - tmp = mmio_readl(spibar + ICH8_REG_VSCC); - msg_pdbg("0x%x: 0x%08x (VSCC)\n", ICH8_REG_VSCC, tmp); - msg_pdbg("VSCC: "); - prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true); - } else { - tmp = mmio_readl(spibar + ICH9_REG_LVSCC); - msg_pdbg("0x%x: 0x%08x (LVSCC)\n", ICH9_REG_LVSCC, tmp); - msg_pdbg("LVSCC: "); - prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true); - - tmp = mmio_readl(spibar + ICH9_REG_UVSCC); - msg_pdbg("0x%x: 0x%08x (UVSCC)\n", ICH9_REG_UVSCC, tmp); - msg_pdbg("UVSCC: "); - prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, false); - } - - switch (ich_gen) { - case CHIPSET_ICH8: - case CHIPSET_100_SERIES_SUNRISE_POINT: - case CHIPSET_C620_SERIES_LEWISBURG: - case CHIPSET_300_SERIES_CANNON_POINT: - case CHIPSET_400_SERIES_COMET_POINT: - case CHIPSET_APOLLO_LAKE: - case CHIPSET_GEMINI_LAKE: - break; - default: - tmp = mmio_readl(spibar + ICH9_REG_FPB); - msg_pdbg("0x%x: 0x%08x (FPB)\n", ICH9_REG_FPB, tmp); - break; - } - - if (read_ich_descriptors_via_fdo(ich_gen, spibar, &desc) == ICH_RET_OK) - prettyprint_ich_descriptors(ich_gen, &desc); - - /* If the descriptor is valid and indicates multiple - * flash devices we need to use hwseq to be able to - * access the second flash device. - */ - if (ich_spi_mode == ich_auto && desc.content.NC != 0) { - msg_pinfo("Enabling hardware sequencing due to " - "multiple flash chips detected.\n"); - ich_spi_mode = ich_hwseq; - } - } - - if (ich_spi_mode == ich_auto && ichspi_lock && - ich_missing_opcodes()) { - msg_pinfo("Enabling hardware sequencing because " - "some important opcode is locked.\n"); - ich_spi_mode = ich_hwseq; - } - - if (ich_spi_mode == ich_auto && - (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT || - ich_gen == CHIPSET_300_SERIES_CANNON_POINT || - ich_gen == CHIPSET_400_SERIES_COMET_POINT)) { - msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n"); - ich_spi_mode = ich_hwseq; - } - - if (ich_spi_mode == ich_auto && - (ich_gen == CHIPSET_APOLLO_LAKE || - ich_gen == CHIPSET_GEMINI_LAKE)) { - msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini Lake.\n"); - ich_spi_mode = ich_hwseq; - } - - if (ich_spi_mode == ich_hwseq) { - if (!desc_valid) { - msg_perr("Hardware sequencing was requested " - "but the flash descriptor is not " - "valid. Aborting.\n"); - return ERROR_FATAL; - } - - int tmpi = getFCBA_component_density(ich_gen, &desc, 0); - if (tmpi < 0) { - msg_perr("Could not determine density of flash component %d.\n", 0); - return ERROR_FATAL; - } - hwseq_data.size_comp0 = tmpi; - - tmpi = getFCBA_component_density(ich_gen, &desc, 1); - if (tmpi < 0) { - msg_perr("Could not determine density of flash component %d.\n", 1); - return ERROR_FATAL; - } - hwseq_data.size_comp1 = tmpi; - - register_opaque_master(&opaque_master_ich_hwseq, NULL); + if (ich_gen == CHIPSET_ICH8) { + tmp = mmio_readl(spibar + ICH8_REG_VSCC); + msg_pdbg("0x%x: 0x%08x (VSCC)\n", ICH8_REG_VSCC, tmp); + msg_pdbg("VSCC: "); + prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true); } else { - register_spi_master(&spi_master_ich9, NULL); + tmp = mmio_readl(spibar + ICH9_REG_LVSCC); + msg_pdbg("0x%x: 0x%08x (LVSCC)\n", ICH9_REG_LVSCC, tmp); + msg_pdbg("LVSCC: "); + prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true); + + tmp = mmio_readl(spibar + ICH9_REG_UVSCC); + msg_pdbg("0x%x: 0x%08x (UVSCC)\n", ICH9_REG_UVSCC, tmp); + msg_pdbg("UVSCC: "); + prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, false); } - break; + + switch (ich_gen) { + case CHIPSET_ICH8: + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: + case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: + break; + default: + tmp = mmio_readl(spibar + ICH9_REG_FPB); + msg_pdbg("0x%x: 0x%08x (FPB)\n", ICH9_REG_FPB, tmp); + break; + } + + if (read_ich_descriptors_via_fdo(ich_gen, spibar, &desc) == ICH_RET_OK) + prettyprint_ich_descriptors(ich_gen, &desc); + + /* If the descriptor is valid and indicates multiple + * flash devices we need to use hwseq to be able to + * access the second flash device. + */ + if (ich_spi_mode == ich_auto && desc.content.NC != 0) { + msg_pinfo("Enabling hardware sequencing due to " + "multiple flash chips detected.\n"); + ich_spi_mode = ich_hwseq; + } + } + + if (ich_spi_mode == ich_auto && ichspi_lock && + ich_missing_opcodes()) { + msg_pinfo("Enabling hardware sequencing because " + "some important opcode is locked.\n"); + ich_spi_mode = ich_hwseq; + } + + if (ich_spi_mode == ich_auto && + (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT || + ich_gen == CHIPSET_300_SERIES_CANNON_POINT || + ich_gen == CHIPSET_400_SERIES_COMET_POINT)) { + msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n"); + ich_spi_mode = ich_hwseq; + } + + if (ich_spi_mode == ich_auto && + (ich_gen == CHIPSET_APOLLO_LAKE || + ich_gen == CHIPSET_GEMINI_LAKE)) { + msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini Lake.\n"); + ich_spi_mode = ich_hwseq; + } + + if (ich_spi_mode == ich_hwseq) { + if (!desc_valid) { + msg_perr("Hardware sequencing was requested " + "but the flash descriptor is not " + "valid. Aborting.\n"); + return ERROR_FATAL; + } + + int tmpi = getFCBA_component_density(ich_gen, &desc, 0); + if (tmpi < 0) { + msg_perr("Could not determine density of flash component %d.\n", 0); + return ERROR_FATAL; + } + hwseq_data.size_comp0 = tmpi; + + tmpi = getFCBA_component_density(ich_gen, &desc, 1); + if (tmpi < 0) { + msg_perr("Could not determine density of flash component %d.\n", 1); + return ERROR_FATAL; + } + hwseq_data.size_comp1 = tmpi; + + register_opaque_master(&opaque_master_ich_hwseq, NULL); + } else { + register_spi_master(&spi_master_ich9, NULL); + } + + return 0; +} + +int ich_init_spi(void *spibar, enum ich_chipset ich_gen) +{ + switch (ich_gen) { + case CHIPSET_ICH7: + case CHIPSET_TUNNEL_CREEK: + case CHIPSET_CENTERTON: + return init_ich7_spi(spibar, ich_gen); + case CHIPSET_ICH8: + default: /* Future version might behave the same */ + return init_ich_default(spibar, ich_gen); } return 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/58735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6789bc456a4878e6555831ae0b80ecbdbf62938b Gerrit-Change-Number: 58735 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips.c: big erase blocksize first
by Simon Buhrow (Code Review) 28 Oct '21

28 Oct '21

Attention is currently required from: Nico Huber, Angel Pons. Simon Buhrow has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58467 ) Change subject: flashchips.c: big erase blocksize first ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Have you tried with random data? You can create a file with random data like this: […] You are right. With your setup writing random_data_2.bin takes much longer with this commit than with origin. So the solution must be much smarter. Furthermore I saw that the erase function is set in walk_by_layout while the per block function is called somewhat deeper. This looks like a good solution will need reorder of steps. I´ll keep trying/thinking of how the steps you mentioned could be implemented. Any suggestions are welcome. @Angel: Thanks a lot for your detailed setup description. That helped me a lot! -- To view, visit https://review.coreboot.org/c/flashrom/+/58467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I862ce0b5f8912565e43c340578d8126aa2e6aa3b Gerrit-Change-Number: 58467 Gerrit-PatchSet: 1 Gerrit-Owner: Simon Buhrow Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 28 Oct 2021 11:43:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Simon Buhrow Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in flashrom[master]: flashrom_tester: Use elogtool to list firmware eventlog
by Angel Pons (Code Review) 27 Oct '21

27 Oct '21

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58527 ) Change subject: flashrom_tester: Use elogtool to list firmware eventlog ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > Can we land it? Sure thing, thanks for the reminder -- To view, visit https://review.coreboot.org/c/flashrom/+/58527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8c4be82fed28b6a19746e6b93fafce23bd8ede5d Gerrit-Change-Number: 58527 Gerrit-PatchSet: 3 Gerrit-Owner: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ricardo Quesada <ricardoq(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 27 Oct 2021 09:13:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: flashrom_tester: Use elogtool to list firmware eventlog
by Angel Pons (Code Review) 27 Oct '21

27 Oct '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/flashrom/+/58527 ) Change subject: flashrom_tester: Use elogtool to list firmware eventlog ...................................................................... flashrom_tester: Use elogtool to list firmware eventlog Mosys is dropping the eventlog command, in favor of the elogtool command provided in coreboot. The output is compatible with what mosys used to output. Signed-off-by: Jack Rosenthal <jrosenth(a)chromium.org> Change-Id: I8c4be82fed28b6a19746e6b93fafce23bd8ede5d Reviewed-on: https://review.coreboot.org/c/flashrom/+/58527 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Ricardo Quesada <ricardoq(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M util/flashrom_tester/src/cros_sysinfo.rs M util/flashrom_tester/src/tests.rs 2 files changed, 7 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved Ricardo Quesada: Looks good to me, but someone else must approve diff --git a/util/flashrom_tester/src/cros_sysinfo.rs b/util/flashrom_tester/src/cros_sysinfo.rs index ddb0802..4d1b347 100644 --- a/util/flashrom_tester/src/cros_sysinfo.rs +++ b/util/flashrom_tester/src/cros_sysinfo.rs @@ -61,13 +61,13 @@ } pub fn eventlog_list() -> Result<String, std::io::Error> { - mosys_dispatch(&["eventlog", "list"]) + elogtool_dispatch(&["list"]) } -fn mosys_dispatch<S: AsRef<OsStr> + Debug>(args: &[S]) -> IoResult<String> { - info!("mosys_dispatch() running: /usr/sbin/mosys {:?}", args); +fn elogtool_dispatch<S: AsRef<OsStr> + Debug>(args: &[S]) -> IoResult<String> { + info!("elogtool_dispatch() running: /usr/bin/elogtool {:?}", args); - let output = Command::new("/usr/sbin/mosys") + let output = Command::new("/usr/bin/elogtool") .args(args) .stdin(Stdio::null()) .output()?; diff --git a/util/flashrom_tester/src/tests.rs b/util/flashrom_tester/src/tests.rs index 9ef98e5..86c0da5 100644 --- a/util/flashrom_tester/src/tests.rs +++ b/util/flashrom_tester/src/tests.rs @@ -234,13 +234,13 @@ fn elog_sanity_test(env: &mut TestEnv) -> TestResult { // Check that the elog contains *something*, as an indication that Coreboot - // is actually able to write to the Flash. Because this invokes mosys on the - // host, it doesn't make sense to run for other chips. + // is actually able to write to the Flash. Because this invokes elogtool on + // the host, it doesn't make sense to run for other chips. if env.chip_type() != FlashChip::HOST { info!("Skipping ELOG sanity check for non-host chip"); return Ok(()); } - // mosys reads the flash, it should be back in the golden state + // elogtool reads the flash, it should be back in the golden state env.ensure_golden()?; // Output is one event per line, drop empty lines in the interest of being defensive. let event_count = cros_sysinfo::eventlog_list()? -- To view, visit https://review.coreboot.org/c/flashrom/+/58527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8c4be82fed28b6a19746e6b93fafce23bd8ede5d Gerrit-Change-Number: 58527 Gerrit-PatchSet: 3 Gerrit-Owner: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ricardo Quesada <ricardoq(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: flashrom_tester: Use elogtool to list firmware eventlog
by Jack Rosenthal (Code Review) 27 Oct '21

27 Oct '21

Attention is currently required from: Furquan Shaikh. Jack Rosenthal has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58527 ) Change subject: flashrom_tester: Use elogtool to list firmware eventlog ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Can we land it? -- To view, visit https://review.coreboot.org/c/flashrom/+/58527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8c4be82fed28b6a19746e6b93fafce23bd8ede5d Gerrit-Change-Number: 58527 Gerrit-PatchSet: 2 Gerrit-Owner: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ricardo Quesada <ricardoq(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Wed, 27 Oct 2021 01:24:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: Makefile: Revise build options for Linux specific headers
by Thomas Heijligen (Code Review) 26 Oct '21

26 Oct '21

Attention is currently required from: Nico Huber, Angel Pons. Hello build bot (Jenkins), Nico Huber, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/58627 to look at the new patch set (#5). Change subject: Makefile: Revise build options for Linux specific headers ...................................................................... Makefile: Revise build options for Linux specific headers Clean up the feature target by outsourcing the test to an own variable. Change the print output and don't write to the build-details file. This is in preparation for further changes. Change-Id: I18fc27252afb49fa7d1f2787faee2b5b669275aa Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M Makefile A Makefile.d/linux_i2c_test.c A Makefile.d/linux_mtd_test.c A Makefile.d/linux_spi_test.c M Makefile.include 5 files changed, 48 insertions(+), 82 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/27/58627/5 -- To view, visit https://review.coreboot.org/c/flashrom/+/58627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I18fc27252afb49fa7d1f2787faee2b5b669275aa Gerrit-Change-Number: 58627 Gerrit-PatchSet: 5 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: Makefile: Revise build options for Linux specific headers
by Thomas Heijligen (Code Review) 26 Oct '21

26 Oct '21

Attention is currently required from: Nico Huber, Angel Pons. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58627 ) Change subject: Makefile: Revise build options for Linux specific headers ...................................................................... Patch Set 4: (2 comments) File Makefile: https://review.coreboot.org/c/flashrom/+/58627/comment/bb6f19cd_325c0cc5 PS2, Line 260: $(call mark_unsupported,CONFIG_MSTARDDC_SPI) > What about realtek_mst_i2c_spi and lspcon_i2c_spi? Done File Makefile.include: https://review.coreboot.org/c/flashrom/+/58627/comment/60728f7d_fcf92b27 PS2, Line 146: #include <linux/types.h> > Please keep this, unless we want to investigate why it was added. Done -- To view, visit https://review.coreboot.org/c/flashrom/+/58627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I18fc27252afb49fa7d1f2787faee2b5b669275aa Gerrit-Change-Number: 58627 Gerrit-PatchSet: 4 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 26 Oct 2021 16:50:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in flashrom[master]: Makefile: Revise build options for Linux specific headers
by Thomas Heijligen (Code Review) 26 Oct '21

26 Oct '21

Attention is currently required from: Thomas Heijligen, Angel Pons. Hello build bot (Jenkins), Nico Huber, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/58627 to look at the new patch set (#4). Change subject: Makefile: Revise build options for Linux specific headers ...................................................................... Makefile: Revise build options for Linux specific headers Clean up the feature target by outsourcing the test to an own variable. Change the print output and don't write to the build-details file. This is in preparation for further changes. Change-Id: I18fc27252afb49fa7d1f2787faee2b5b669275aa Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M Makefile A Makefile.d/linux_i2c_test.c A Makefile.d/linux_mtd_test.c A Makefile.d/linux_spi_test.c M Makefile.include 5 files changed, 47 insertions(+), 80 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/27/58627/4 -- To view, visit https://review.coreboot.org/c/flashrom/+/58627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I18fc27252afb49fa7d1f2787faee2b5b669275aa Gerrit-Change-Number: 58627 Gerrit-PatchSet: 4 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: Makefile: Revise build options for Linux specific headers
by Nico Huber (Code Review) 26 Oct '21

26 Oct '21

Attention is currently required from: Thomas Heijligen, Angel Pons. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58627 ) Change subject: Makefile: Revise build options for Linux specific headers ...................................................................... Patch Set 2: (2 comments) File Makefile: https://review.coreboot.org/c/flashrom/+/58627/comment/bdb397c5_943871bb PS2, Line 260: $(call mark_unsupported,CONFIG_MSTARDDC_SPI) What about realtek_mst_i2c_spi and lspcon_i2c_spi? File Makefile.include: https://review.coreboot.org/c/flashrom/+/58627/comment/1db5dcdb_2fe14780 PS2, Line 146: #include <linux/types.h> Please keep this, unless we want to investigate why it was added. -- To view, visit https://review.coreboot.org/c/flashrom/+/58627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I18fc27252afb49fa7d1f2787faee2b5b669275aa Gerrit-Change-Number: 58627 Gerrit-PatchSet: 2 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 26 Oct 2021 16:32:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: Makefile: Revise build options for Linux specific headers
by Thomas Heijligen (Code Review) 26 Oct '21

26 Oct '21

Attention is currently required from: Nico Huber, Angel Pons. Hello build bot (Jenkins), Nico Huber, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/58627 to look at the new patch set (#3). Change subject: Makefile: Revise build options for Linux specific headers ...................................................................... Makefile: Revise build options for Linux specific headers Clean up the feature target by outsourcing the test to an own variable. Change the print output and don't write to the build-details file. This is in preparation for further changes. Change-Id: I18fc27252afb49fa7d1f2787faee2b5b669275aa Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M Makefile A Makefile.d/linux_i2c_test.c A Makefile.d/linux_mtd_test.c A Makefile.d/linux_spi_test.c M Makefile.include 5 files changed, 50 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/27/58627/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/58627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I18fc27252afb49fa7d1f2787faee2b5b669275aa Gerrit-Change-Number: 58627 Gerrit-PatchSet: 3 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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