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Hello Felix Singer, build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58134
to look at the new patch set (#4).
Change subject: flashchips: Add Puya P25Q21H/11H/06H
......................................................................
flashchips: Add Puya P25Q21H/11H/06H
Datasheet:
https://datasheet.lcsc.com/szlcsc/1908281813_PUYA-P25Q21H-SSH-IT_C414061.pdf
Tested P25Q21H read, write and probe with CH341a.
Signed-off-by: Nita Vesa <werecatf(a)outlook.com>
Change-Id: Idd43145c72607837cb7afa1b007e68eb8e63ebd9
---
M flashchips.c
M flashchips.h
2 files changed, 134 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/58134/4
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WereCatf has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58134 )
Change subject: flashchips: Add Puya P25Q21H/11H/06H
......................................................................
Patch Set 3:
(6 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/58134/comment/749dae56_fbfa9f8b
PS2, Line 10: https://datasheet.lcsc.com/szlcsc/1908281813_PUYA-P25Q21H-SSH-IT_C414061.pdf
> While we're at it, I'd greatly appreciate if you could add support for the P25Q11H and P25Q06H as we […]
Done
Patchset:
PS3:
Requested changes made.
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/58134/comment/d56bd9b9_f640bc0b
PS2, Line 13158: }, {
> Missing entries for the full chip erase commands: […]
Done
https://review.coreboot.org/c/flashrom/+/58134/comment/cc69cdb7_829d2966
PS2, Line 13158:
: .eraseblocks = { {256, 1024} },
: .block_erase = spi_block_erase_81
> Block eraser entries should be sorted in ascending block size (the pair of numbers is `{ block size, […]
Done
https://review.coreboot.org/c/flashrom/+/58134/comment/44b2bd1d_216d4e58
PS2, Line 13163: spi_prettyprint_status_register_plain
> spi_prettyprint_status_register_bp4_srwd
Done
https://review.coreboot.org/c/flashrom/+/58134/comment/f3c102e1_6fcbe5d0
PS2, Line 13164: spi_disable_blockprotect
> spi_disable_blockprotect_bp4_srwd
Done
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Attention is currently required from: Felix Singer, WereCatf.
Hello Felix Singer, build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58134
to look at the new patch set (#3).
Change subject: flashchips: Add Puya P25Q21H/11H/06H
......................................................................
flashchips: Add Puya P25Q21H/11H/06H
Datasheet:
https://datasheet.lcsc.com/szlcsc/1908281813_PUYA-P25Q21H-SSH-IT_C414061.pdf
Tested read, write and probe with CH341a.
Signed-off-by: Nita Vesa <werecatf(a)outlook.com>
Change-Id: Idd43145c72607837cb7afa1b007e68eb8e63ebd9
---
M flashchips.c
M flashchips.h
2 files changed, 134 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/58134/3
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/57975 )
Change subject: raiden_debug_spi: Use new API to register shutdown function
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/57975/comment/d87d95d0_c146eada
PS2, Line 17: TRY TO TEST ME ON HW
I guess this is why I didn't give a +2 yet. Any plans to do this
before we merge these patches?
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Change subject: raiden_debug_spi: Use spi data in configure_protocol
......................................................................
Patch Set 2: Code-Review+2
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Change subject: raiden_debug_spi: Link spi_master struct to spi data
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File raiden_debug_spi.c:
https://review.coreboot.org/c/flashrom/+/57972/comment/70665b41_e9717435
PS2, Line 1404: free(ctx_data);
: free(spi_config);
> spi_config is independent pointer and it won't disappear after free(ctx_data)?
That's it. Both pointers live on the stack.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58134 )
Change subject: flashchips: Add Puya P25Q21H
......................................................................
Patch Set 2: Code-Review+1
(5 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/58134/comment/5de4d4c9_f171e66c
PS2, Line 10: https://datasheet.lcsc.com/szlcsc/1908281813_PUYA-P25Q21H-SSH-IT_C414061.pdf
While we're at it, I'd greatly appreciate if you could add support for the P25Q11H and P25Q06H as well, as they only differ in size (`total_size` and `block_erasers` need adjustment). Also, they should be marked as `TEST_UNTESTED` for now.
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/58134/comment/afce1fd9_dc732ce9
PS2, Line 13158: }, {
Missing entries for the full chip erase commands:
}, {
.eraseblocks = { {256 * 1024, 1} },
.block_erase = spi_block_erase_60,
}, {
.eraseblocks = { {256 * 1024, 1} },
.block_erase = spi_block_erase_c7,
},
These two entries should be the last, below the other entries.
https://review.coreboot.org/c/flashrom/+/58134/comment/61ccc19b_f8bd1e02
PS2, Line 13158:
: .eraseblocks = { {256, 1024} },
: .block_erase = spi_block_erase_81
Block eraser entries should be sorted in ascending block size (the pair of numbers is `{ block size, number of blocks }`). So, this one should be the first, above the other entries.
I expect this change to slow down erasing/rewriting. If the performance impact is unacceptable (e.g. full erase time goes from several seconds to some minutes), please let me know.
https://review.coreboot.org/c/flashrom/+/58134/comment/aeb31eda_819dad41
PS2, Line 13163: spi_prettyprint_status_register_plain
spi_prettyprint_status_register_bp4_srwd
https://review.coreboot.org/c/flashrom/+/58134/comment/65130650_1bc05f2d
PS2, Line 13164: spi_disable_blockprotect
spi_disable_blockprotect_bp4_srwd
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Change subject: flashchips: Add Puya P25Q21H
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/58134/comment/2d3f4227_06fbe44f
PS1, Line 8:
> Please add a link to the datasheet and explain how you tested it.
Done
Patchset:
PS2:
The chip is apparently actually called P25Q21H, despite the markings on it saying P25D21H, so I changed that. Also, I did add the requested changes to the commit-message.
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Hanno Heinrichs has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/51048 )
Change subject: flashchips: Add AT25DF011
......................................................................
Patch Set 5:
(4 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/51048/comment/d8d48962_50aa366b
PS4, Line 10:
> Please add a link to the datasheet.
Ack
Patchset:
PS5:
Thank you all for your feedback. I think I have taken care of all points.
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/51048/comment/d8a904ac_cdf26e23
PS2, Line 1495: TEST_OK_PREW
> Maybe add some details to the commit message about how you tested the chip.
Ack
https://review.coreboot.org/c/flashrom/+/51048/comment/24aab1d4_2524c730
PS2, Line 1521: /* 2.3-3.6V & 2.7-3.6V models available */
> The DS-25DF011–032F–5/2017 datasheet states that the range is 1.65v-3.6v.
Ack, Thank you for your feedback and please excuse the delay!
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Hello Felix Singer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58134
to look at the new patch set (#2).
Change subject: flashchips: Add Puya P25Q21H
......................................................................
flashchips: Add Puya P25Q21H
Datasheet:
https://datasheet.lcsc.com/szlcsc/1908281813_PUYA-P25Q21H-SSH-IT_C414061.pdf
Tested read, write and probe with CH341a.
Signed-off-by: Nita Vesa <werecatf(a)outlook.com>
Change-Id: Idd43145c72607837cb7afa1b007e68eb8e63ebd9
---
M flashchips.c
M flashchips.h
2 files changed, 40 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/58134/2
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