Attention is currently required from: Felix Singer, WereCatf. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58134 )
Change subject: flashchips: Add Puya P25Q21H ......................................................................
Patch Set 2: Code-Review+1
(5 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/58134/comment/5de4d4c9_f171e66c PS2, Line 10: https://datasheet.lcsc.com/szlcsc/1908281813_PUYA-P25Q21H-SSH-IT_C414061.pdf While we're at it, I'd greatly appreciate if you could add support for the P25Q11H and P25Q06H as well, as they only differ in size (`total_size` and `block_erasers` need adjustment). Also, they should be marked as `TEST_UNTESTED` for now.
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/58134/comment/afce1fd9_dc732ce9 PS2, Line 13158: }, { Missing entries for the full chip erase commands:
}, { .eraseblocks = { {256 * 1024, 1} }, .block_erase = spi_block_erase_60, }, { .eraseblocks = { {256 * 1024, 1} }, .block_erase = spi_block_erase_c7, },
These two entries should be the last, below the other entries.
https://review.coreboot.org/c/flashrom/+/58134/comment/61ccc19b_f8bd1e02 PS2, Line 13158: : .eraseblocks = { {256, 1024} }, : .block_erase = spi_block_erase_81 Block eraser entries should be sorted in ascending block size (the pair of numbers is `{ block size, number of blocks }`). So, this one should be the first, above the other entries.
I expect this change to slow down erasing/rewriting. If the performance impact is unacceptable (e.g. full erase time goes from several seconds to some minutes), please let me know.
https://review.coreboot.org/c/flashrom/+/58134/comment/aeb31eda_819dad41 PS2, Line 13163: spi_prettyprint_status_register_plain spi_prettyprint_status_register_bp4_srwd
https://review.coreboot.org/c/flashrom/+/58134/comment/65130650_1bc05f2d PS2, Line 13164: spi_disable_blockprotect spi_disable_blockprotect_bp4_srwd
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Angel Pons (Code Review)