January 2021 - flashrom-gerrit

Change in flashrom[master]: rayer_spi.c: Implement `set_sck_set_mosi` operation
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/49265 ) Change subject: rayer_spi.c: Implement `set_sck_set_mosi` operation ...................................................................... rayer_spi.c: Implement `set_sck_set_mosi` operation Change-Id: Ieb05a35967685c2444d064cb61cec98e2a00f590 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M rayer_spi.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/65/49265/1 diff --git a/rayer_spi.c b/rayer_spi.c index 8e869e6..8c7f53e 100644 --- a/rayer_spi.c +++ b/rayer_spi.c @@ -147,6 +147,15 @@ OUTB(lpt_outbyte, lpt_iobase); } +static void rayer_bitbang_set_sck_set_mosi(int sck, int mosi) +{ + lpt_outbyte &= ~(1 << pinout->sck_bit); + lpt_outbyte &= ~(1 << pinout->mosi_bit); + lpt_outbyte |= (sck << pinout->sck_bit); + lpt_outbyte |= (mosi << pinout->mosi_bit); + OUTB(lpt_outbyte, lpt_iobase); +} + static int rayer_bitbang_get_miso(void) { uint8_t tmp; @@ -160,6 +169,7 @@ .set_cs = rayer_bitbang_set_cs, .set_sck = rayer_bitbang_set_sck, .set_mosi = rayer_bitbang_set_mosi, + .set_sck_set_mosi = rayer_bitbang_set_sck_set_mosi, .get_miso = rayer_bitbang_get_miso, .half_period = 0, }; -- To view, visit https://review.coreboot.org/c/flashrom/+/49265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ieb05a35967685c2444d064cb61cec98e2a00f590 Gerrit-Change-Number: 49265 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: lspcon_i2c_spi.c: Make consistent with std=c99
by Edward O'Callaghan (Code Review) 10 Jan '21

10 Jan '21

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47910 ) Change subject: lspcon_i2c_spi.c: Make consistent with std=c99 ...................................................................... lspcon_i2c_spi.c: Make consistent with std=c99 Use 'modern' C to scope iterator declarations only to the loop constructs they are used in. BUG=none TEST=builds Change-Id: Id61f8416416d2f625d424760e00f94dc730105f4 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M lspcon_i2c_spi.c 1 file changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/10/47910/1 diff --git a/lspcon_i2c_spi.c b/lspcon_i2c_spi.c index 7b9f1c0..6ee2840 100644 --- a/lspcon_i2c_spi.c +++ b/lspcon_i2c_spi.c @@ -127,14 +127,13 @@ static int lspcon_i2c_spi_register_control(int fd, packet_t *packet) { - int i; int ret = lspcon_i2c_spi_write_register(fd, SWSPI_WDATA, packet->command); if (ret) return ret; /* Higher 4 bits are read size. */ int write_size = packet->data_size & 0x0f; - for (i = 0; i < write_size; ++i) { + for (unsigned i = 0; i < write_size; ++i) { ret |= lspcon_i2c_spi_write_register(fd, SWSPI_WDATA, packet->data[i]); } @@ -256,7 +255,6 @@ const unsigned char *writearr, unsigned char *readarr) { - unsigned int i; if (writecnt > 16 || readcnt > 16 || writecnt == 0) { msg_perr("%s: Invalid read/write count for send command.\n", __func__); @@ -285,7 +283,7 @@ if (ret) return ret; - for (i = 0; i < readcnt; ++i) { + for (unsigned i = 0; i < readcnt; ++i) { ret |= lspcon_i2c_spi_read_register(fd, SWSPI_RDATA, &readarr[i]); } @@ -340,7 +338,6 @@ static int lspcon_i2c_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) { - unsigned int i; int ret = 0; if (start & 0xff) return default_spi_read(flash, buf, start, len); @@ -349,7 +346,7 @@ if (fd < 0) return SPI_GENERIC_ERROR; - for (i = 0; i < len; i += PAGE_SIZE) { + for (unsigned i = 0; i < len; i += PAGE_SIZE) { ret |= lspcon_i2c_spi_map_page(fd, start + i); ret |= lspcon_i2c_spi_read_data(fd, PAGE_ADDRESS, buf + i, min(len - i, PAGE_SIZE)); } -- To view, visit https://review.coreboot.org/c/flashrom/+/47910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id61f8416416d2f625d424760e00f94dc730105f4 Gerrit-Change-Number: 47910 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: realtek_mst_i2c_spi.c: Make consistent with std=c99
by Edward O'Callaghan (Code Review) 10 Jan '21

10 Jan '21

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47909 ) Change subject: realtek_mst_i2c_spi.c: Make consistent with std=c99 ...................................................................... realtek_mst_i2c_spi.c: Make consistent with std=c99 Use 'modern' C to scope iterator declarations only to the loop constructs they are used in. BUG=none TEST=builds Change-Id: I9d9d1bf01209a7840f7b3fa2c6f7592375a74330 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M realtek_mst_i2c_spi.c 1 file changed, 4 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/09/47909/1 diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 538b07a..151f7f6 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -205,7 +205,6 @@ const unsigned char *writearr, unsigned char *readarr) { - unsigned i; int max_timeout_mul = 1; int ret = 0; @@ -262,7 +261,7 @@ ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, ctrl_reg_val); ret |= realtek_mst_i2c_spi_write_register(fd, 0x61, writearr[0]); /* opcode */ - for (i = 0; i < writecnt; ++i) + for (unsigned i = 0; i < writecnt; ++i) ret |= realtek_mst_i2c_spi_write_register(fd, 0x64 + i, writearr[i + 1]); ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, ctrl_reg_val | 0x1); if (ret) @@ -272,7 +271,7 @@ if (ret) return ret; - for (i = 0; i < readcnt; ++i) + for (unsigned i = 0; i < readcnt; ++i) ret |= realtek_mst_i2c_spi_read_register(fd, 0x67 + i, &readarr[i]); return ret; @@ -306,7 +305,6 @@ static int realtek_mst_i2c_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) { - unsigned i; int ret = 0; if (start & 0xff) @@ -339,7 +337,7 @@ uint8_t dummy; realtek_mst_i2c_spi_read_register(fd, MCU_DATA_PORT, &dummy); - for (i = 0; i < len; i += PAGE_SIZE) { + for (unsigned i = 0; i < len; i += PAGE_SIZE) { ret |= realtek_mst_i2c_spi_read_data(fd, REGISTER_ADDRESS, buf + i, min(len - i, PAGE_SIZE)); if (ret) @@ -352,7 +350,6 @@ static int realtek_mst_i2c_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len) { - unsigned i; int ret = 0; if (start & 0xff) @@ -369,7 +366,7 @@ ret |= realtek_mst_i2c_spi_write_register(fd, 0x6D, 0x02); /* write opcode */ ret |= realtek_mst_i2c_spi_write_register(fd, 0x71, (PAGE_SIZE - 1)); /* fit len=256 */ - for (i = 0; i < len; i += PAGE_SIZE) { + for (unsigned i = 0; i < len; i += PAGE_SIZE) { uint16_t page_len = min(len - i, PAGE_SIZE); if (len - i < PAGE_SIZE) ret |= realtek_mst_i2c_spi_write_register(fd, 0x71, page_len-1); -- To view, visit https://review.coreboot.org/c/flashrom/+/47909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9d9d1bf01209a7840f7b3fa2c6f7592375a74330 Gerrit-Change-Number: 47909 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: bitbang_spi.c: fix bitbang_spi_send_command to make the delay symmetric
by Xiang Wang (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Stefan Reinauer, Angel Pons. Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/49262 ) Change subject: bitbang_spi.c: fix bitbang_spi_send_command to make the delay symmetric ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/49262/comment/f04c6f67_e23e6111 PS9, Line 7: fix > What is being fixed? In other words, how did you test this? Please mention it in the commit message. There are no bugs, just for better timing. -- To view, visit https://review.coreboot.org/c/flashrom/+/49262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Icf8b65aed20244ccffc231da2c599c6ca1796104 Gerrit-Change-Number: 49262 Gerrit-PatchSet: 11 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shawn C <citypw(a)hardenedlinux.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 10 Jan 2021 13:51:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in flashrom[master]: bitbang_spi.c: fix spi sequence in time
by Xiang Wang (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Stefan Reinauer, Edward O'Callaghan, Angel Pons. Hello build bot (Jenkins), Stefan Reinauer, Edward O'Callaghan, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/49264 to look at the new patch set (#2). Change subject: bitbang_spi.c: fix spi sequence in time ...................................................................... bitbang_spi.c: fix spi sequence in time SPI write operation requires the change of mosi before the change of sck. For this reason, the interface set_sck_set_mosi was rename to set_mosi_set_sck. And the sequence in time bug was corrected. Change-Id: I107803afef044996c94ebfaf0b0e0040cea9f8c1 Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M bitbang_spi.c M developerbox_spi.c M programmer.h 3 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/49264/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/49264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I107803afef044996c94ebfaf0b0e0040cea9f8c1 Gerrit-Change-Number: 49264 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shawn C <citypw(a)hardenedlinux.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: bitbang-spi.c: support clock polarity and phase
by Xiang Wang (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Stefan Reinauer, Edward O'Callaghan, Angel Pons. Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/49255 ) Change subject: bitbang-spi.c: support clock polarity and phase ...................................................................... Patch Set 16: (4 comments) File bitbang_spi.c: https://review.coreboot.org/c/flashrom/+/49255/comment/db8db323_4c4d4f75 PS14, Line 74: bitbang_spi_set_sck_set_mosi > Where did this go? read operate don't care mosi. The previous code is problematic. https://review.coreboot.org/c/flashrom/+/49255/comment/2040673c_b3a40d5e PS14, Line 53: master->set_sck(val); > For sanity's sake, only use `cpol` here. This obscures the meaning https://review.coreboot.org/c/flashrom/+/49255/comment/19b6fb57_11b88c63 PS14, Line 68: bitbang_spi_set_sck_set_mosi > If you're reordering the operations inside this function, I would also rename everything accordingly […] https://review.coreboot.org/c/flashrom/+/49264 https://review.coreboot.org/c/flashrom/+/49255/comment/0672fef7_146ed232 PS14, Line 210: ERROR_FLASHROM_BUG > Definitely not a flashrom bug. I am not very clear, the previous code used this to put back the value -- To view, visit https://review.coreboot.org/c/flashrom/+/49255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I04c1dfe132d756119229b27c3cd611d1be1abc8d Gerrit-Change-Number: 49255 Gerrit-PatchSet: 16 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shawn C <citypw(a)hardenedlinux.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 10 Jan 2021 13:46:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in flashrom[master]: bitbang_spi.c: fix spi sequence in time
by Xiang Wang (Code Review) 10 Jan '21

10 Jan '21

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/49264 ) Change subject: bitbang_spi.c: fix spi sequence in time ...................................................................... bitbang_spi.c: fix spi sequence in time SPI write operation requires the change of mosi before the change of sck. For this reason, the interface set_sck_set_mosi was rename to set_mosi_set_sck. And the sequence in time bug was corrected. Change-Id: I107803afef044996c94ebfaf0b0e0040cea9f8c1 Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M bitbang_spi.c M developerbox_spi.c M programmer.h 3 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/49264/1 diff --git a/bitbang_spi.c b/bitbang_spi.c index 7b69946..c5b2cd0 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -65,15 +65,15 @@ master->release_bus(); } -static void bitbang_spi_set_sck_set_mosi(const struct bitbang_spi_master * const master, int sck, int mosi) +static void bitbang_spi_set_mosi_set_sck(const struct bitbang_spi_master * const master, int mosi, int sck) { - if (master->set_sck_set_mosi) { - master->set_sck_set_mosi(sck, mosi); + if (master->set_mosi_set_sck) { + master->set_mosi_set_sck(mosi, sck); return; } - master->set_sck(sck); master->set_mosi(mosi); + master->set_sck(sck); } static int bitbang_spi_set_sck_get_miso(const struct bitbang_spi_master * const master, int sck) @@ -115,11 +115,11 @@ if (cpha) { bitbang_spi_set_sck(master, !cpol); programmer_delay(master->half_period); - bitbang_spi_set_sck_set_mosi(master, cpol, (val >> i) & 1); + bitbang_spi_set_mosi_set_sck(master, (val >> i) & 1, cpol); programmer_delay(master->half_period); } else { programmer_delay(master->half_period); - bitbang_spi_set_sck_set_mosi(master, !cpol, (val >> i) & 1); + bitbang_spi_set_mosi_set_sck(master, (val >> i) & 1, !cpol); programmer_delay(master->half_period); bitbang_spi_set_sck(master, cpol); } diff --git a/developerbox_spi.c b/developerbox_spi.c index 4ff2fb6..03baba9 100644 --- a/developerbox_spi.c +++ b/developerbox_spi.c @@ -114,7 +114,7 @@ return !!(cp210x_gpio_get() & (1 << DEVELOPERBOX_SPI_MISO)); } -static void cp210x_bitbang_set_sck_set_mosi(int sck, int mosi) +static void cp210x_bitbang_set_mosi_set_sck(int mosi, int sck) { cp210x_gpio_set(sck << DEVELOPERBOX_SPI_SCK | mosi << DEVELOPERBOX_SPI_MOSI, 1 << DEVELOPERBOX_SPI_SCK | 1 << DEVELOPERBOX_SPI_MOSI); @@ -125,7 +125,7 @@ .set_sck = cp210x_bitbang_set_sck, .set_mosi = cp210x_bitbang_set_mosi, .get_miso = cp210x_bitbang_get_miso, - .set_sck_set_mosi = cp210x_bitbang_set_sck_set_mosi, + .set_mosi_set_sck = cp210x_bitbang_set_mosi_set_sck, }; static int developerbox_spi_shutdown(void *data) diff --git a/programmer.h b/programmer.h index 5dbbaf9..aea1419 100644 --- a/programmer.h +++ b/programmer.h @@ -192,7 +192,7 @@ void (*request_bus) (void); void (*release_bus) (void); /* optional functions to optimize xfers */ - void (*set_sck_set_mosi) (int sck, int mosi); + void (*set_mosi_set_sck) (int mosi, int sck); int (*set_sck_get_miso) (int sck); /* Length of half a clock period in usecs. */ unsigned int half_period; -- To view, visit https://review.coreboot.org/c/flashrom/+/49264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I107803afef044996c94ebfaf0b0e0040cea9f8c1 Gerrit-Change-Number: 49264 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: bitbang-spi.c: support clock polarity and phase
by Xiang Wang (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Xiang Wang, Stefan Reinauer, Edward O'Callaghan. Hello build bot (Jenkins), Stefan Reinauer, Edward O'Callaghan, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/49255 to look at the new patch set (#16). Change subject: bitbang-spi.c: support clock polarity and phase ...................................................................... bitbang-spi.c: support clock polarity and phase SPI has four modes, which are determined by Clock polarity and Clock phase. See https://en.wikipedia.org/wiki/Serial_Peripheral_Interface#Clock_polarity_an… for details. The previous code only supports one mode and may not be able to handle some special spi flash. This patch uses spi's mode0 by default to be consistent with the previous code. TEST=build and run flashrom with sysfsgpio on raspberrypi to read W25Q128.V Change-Id: I04c1dfe132d756119229b27c3cd611d1be1abc8d Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M bitbang_spi.c 1 file changed, 69 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/55/49255/16 -- To view, visit https://review.coreboot.org/c/flashrom/+/49255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I04c1dfe132d756119229b27c3cd611d1be1abc8d Gerrit-Change-Number: 49255 Gerrit-PatchSet: 16 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shawn C <citypw(a)hardenedlinux.org> Gerrit-Attention: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: sysfsgpio.c implement spi interface via linux sysfs
by Xiang Wang (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Stefan Reinauer, Angel Pons. Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/49254 ) Change subject: sysfsgpio.c implement spi interface via linux sysfs ...................................................................... Patch Set 5: (8 comments) File Makefile: https://review.coreboot.org/c/flashrom/+/49254/comment/16cd8007_5cc0f179 PS4, Line 800: : CONFIG_SYSFSGPIO ?= no > nit: move this above CONFIG_PRINT_WIKI Done File meson.build: https://review.coreboot.org/c/flashrom/+/49254/comment/25eea8e4_98649e4c PS4, Line 71: config_sysfsgpio > We don't use this anywhere. Done https://review.coreboot.org/c/flashrom/+/49254/comment/2edac7d1_0382b30b PS4, Line 313: if host_machine.system() == 'linux' > Maybe it should be used here. Also, this depends on `config_bitbang_spi`. […] Done File sysfsgpio.c: https://review.coreboot.org/c/flashrom/+/49254/comment/3c5cea59_69a56efe PS4, Line 93: snprintf(s, sizeof(s), "/sys/class/gpio/gpio%s/", desc->pin); > Hmmm... I think you should be able to define the common prefix in a macro and do the following: […] Done https://review.coreboot.org/c/flashrom/+/49254/comment/66a95047_61aecfd3 PS4, Line 111: } I want to know why not use snprintf. The changes you hope will make the code messier. https://review.coreboot.org/c/flashrom/+/49254/comment/d910dd74_3b6bc0c9 PS4, Line 99: snprintf(s, sizeof(s), "/sys/class/gpio/gpio%s/direction", desc->pin); : desc->fd_direction = open(s, O_WRONLY); : if (desc->fd_direction < 0) { : msg_perr("Error: failed to open %s\n", s); : return -1; : } : : snprintf(s, sizeof(s), "/sys/class/gpio/gpio%s/value", desc->pin); : desc->fd_value = open(s, O_RDONLY); : if (desc->fd_value < 0) { : msg_perr("Error: failed to open %s\n", s); : return -1; : } > Here, you could do the following instead: […] I want to know why not use snprintf. The changes you hope will make the code messier. https://review.coreboot.org/c/flashrom/+/49254/comment/e5bf11da_b4b78c89 PS4, Line 135: desc->fd_direction = -1; > Also invalidate the pin string: […] Done https://review.coreboot.org/c/flashrom/+/49254/comment/4c24595a_d32f10c0 PS4, Line 204: static int parse_pins(struct sysfsgpio_pins *pins) > if (v < 0 || v > 9999999) > break 99999 is a large enough number, but I don’t think there is a speed requirement here. You can hand it to export_sysfsgpio to determine whether the value of v is valid. > const long v = strtol(token, &suffix, 10); I don’t think it is necessary to limit the use of decimal numbers -- To view, visit https://review.coreboot.org/c/flashrom/+/49254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1bc47ef8011bba560326b501a80869340bb9f733 Gerrit-Change-Number: 49254 Gerrit-PatchSet: 5 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Shawn C <citypw(a)hardenedlinux.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 10 Jan 2021 13:17:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in flashrom[master]: sysfsgpio.c implement spi interface via linux sysfs
by Xiang Wang (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Xiang Wang, Stefan Reinauer. Hello build bot (Jenkins), Stefan Reinauer, Edward O'Callaghan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/49254 to look at the new patch set (#5). Change subject: sysfsgpio.c implement spi interface via linux sysfs ...................................................................... sysfsgpio.c implement spi interface via linux sysfs Linux can operate gpio through sysfs, this patch implements a bitbang spi interface through sysfs. Through this patch, some SBC can be used as flash programmers. TEST=build and run flashrom with sysfsgpio on raspberrypi to read W25Q128.V Change-Id: I1bc47ef8011bba560326b501a80869340bb9f733 Signed-off-by: Xiang Wang <merle(a)hardenedliux.org> --- M Makefile M flashrom.c M meson.build M programmer.h A sysfsgpio.c 5 files changed, 278 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/49254/5 -- To view, visit https://review.coreboot.org/c/flashrom/+/49254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1bc47ef8011bba560326b501a80869340bb9f733 Gerrit-Change-Number: 49254 Gerrit-PatchSet: 5 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Shawn C <citypw(a)hardenedlinux.org> Gerrit-Attention: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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