January 2021 - flashrom-gerrit

Change in flashrom[master]: sysfsgpio.c implement spi interface via linux sysfs
by Xiang Wang (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Stefan Reinauer, Angel Pons. Hello build bot (Jenkins), Stefan Reinauer, Edward O'Callaghan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/49254 to look at the new patch set (#6). Change subject: sysfsgpio.c implement spi interface via linux sysfs ...................................................................... sysfsgpio.c implement spi interface via linux sysfs Linux can operate gpio through sysfs, this patch implements a bitbang spi interface through sysfs. Through this patch, some SBC can be used as flash programmers. TEST=build and run flashrom with sysfsgpio on raspberrypi to read W25Q128.V Change-Id: I1bc47ef8011bba560326b501a80869340bb9f733 Signed-off-by: Xiang Wang <merle(a)hardenedliux.org> --- M Makefile M flashrom.c M meson.build M programmer.h A sysfsgpio.c 5 files changed, 279 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/49254/6 -- To view, visit https://review.coreboot.org/c/flashrom/+/49254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1bc47ef8011bba560326b501a80869340bb9f733 Gerrit-Change-Number: 49254 Gerrit-PatchSet: 6 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Shawn C <citypw(a)hardenedlinux.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: [UNTESTED] bitbang_spi.c: Support changing clock polarity and phase
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Xiang Wang. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/49271 ) Change subject: [UNTESTED] bitbang_spi.c: Support changing clock polarity and phase ...................................................................... Patch Set 1: (1 comment) File bitbang_spi.c: https://review.coreboot.org/c/flashrom/+/49271/comment/704c2248_903afe61 PS1, Line 71: cpha > I think you need to take a closer look at https://en.wikipedia. […] Have you tested this patch? Note that the clock phase is conditionally shifted in `bitbang_spi_send_command()`. -- To view, visit https://review.coreboot.org/c/flashrom/+/49271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I415a528c013f1a523e883d812b6890be39bfcc7b Gerrit-Change-Number: 49271 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-Attention: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-Comment-Date: Sun, 10 Jan 2021 14:13:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: comment

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Change in flashrom[master]: [UNTESTED] bitbang_spi.c: Support changing clock polarity and phase
by Xiang Wang (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Angel Pons. Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/49271 ) Change subject: [UNTESTED] bitbang_spi.c: Support changing clock polarity and phase ...................................................................... Patch Set 1: (1 comment) File bitbang_spi.c: https://review.coreboot.org/c/flashrom/+/49271/comment/d5e6e3ce_ec6d4f99 PS1, Line 71: cpha I think you need to take a closer look at https://en.wikipedia.org/wiki/Serial_Peripheral_Interface#Clock_polarity_an…. cpha does not mean this. -- To view, visit https://review.coreboot.org/c/flashrom/+/49271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I415a528c013f1a523e883d812b6890be39bfcc7b Gerrit-Change-Number: 49271 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 10 Jan 2021 14:06:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: bitbang-spi.c: support clock polarity and phase
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Attention is currently required from: Xiang Wang, Stefan Reinauer, Edward O'Callaghan. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/49255 ) Change subject: bitbang-spi.c: support clock polarity and phase ...................................................................... Patch Set 16: (1 comment) Patchset: PS16: I ended up making a separate patch train: https://review.coreboot.org/q/topic:"bitbang-spi-clock-modes" -- To view, visit https://review.coreboot.org/c/flashrom/+/49255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I04c1dfe132d756119229b27c3cd611d1be1abc8d Gerrit-Change-Number: 49255 Gerrit-PatchSet: 16 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shawn C <citypw(a)hardenedlinux.org> Gerrit-Attention: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Sun, 10 Jan 2021 13:58:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: [UNTESTED] bitbang_spi.c: Support changing clock polarity and phase
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/49271 ) Change subject: [UNTESTED] bitbang_spi.c: Support changing clock polarity and phase ...................................................................... [UNTESTED] bitbang_spi.c: Support changing clock polarity and phase Change-Id: I415a528c013f1a523e883d812b6890be39bfcc7b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M bitbang_spi.c 1 file changed, 45 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/71/49271/1 diff --git a/bitbang_spi.c b/bitbang_spi.c index 00c631f..252adab 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -21,6 +21,9 @@ #include "programmer.h" #include "spi.h" +static int cpol = 0; /* Clock Polarity */ +static int cpha = 0; /* Clock Phase */ + /* Note that CS# is active low, so val=0 means the chip is active. */ static void bitbang_spi_set_cs(const struct bitbang_spi_master * const master, int val) { @@ -29,7 +32,7 @@ static void bitbang_spi_set_sck(const struct bitbang_spi_master * const master, int val) { - master->set_sck(val); + master->set_sck(val ^ cpol); } static void bitbang_spi_request_bus(const struct bitbang_spi_master * const master) @@ -54,6 +57,10 @@ return master->set_sck_get_miso(sck); } +/* + * For CPHA=0, the "in" side captures the data on (or shortly after) the leading edge of the clock cycle. + * For CPHA=1, the "in" side captures the data on (or shortly after) the trailing edge of the clock cycle. + */ static uint8_t bitbang_spi_read_byte(const struct bitbang_spi_master *master) { uint8_t ret = 0; @@ -61,25 +68,29 @@ for (i = 7; i >= 0; i--) { if (i == 0) - bitbang_spi_set_mosi_set_sck(master, 0, 0); + bitbang_spi_set_mosi_set_sck(master, 0, cpha); else bitbang_spi_set_sck(master, 0); programmer_delay(master->half_period); ret <<= 1; - ret |= bitbang_spi_set_sck_get_miso(master, 1); + ret |= bitbang_spi_set_sck_get_miso(master, !cpha); programmer_delay(master->half_period); } return ret; } +/* + * For CPHA=0, the "out" side changes the data on the trailing edge of the preceding clock cycle. + * For CPHA=1, the "out" side changes the data on the leading edge of the current clock cycle. + */ static void bitbang_spi_write_byte(const struct bitbang_spi_master *master, uint8_t val) { int i; for (i = 7; i >= 0; i--) { - bitbang_spi_set_mosi_set_sck(master, (val >> i) & 1, 0); + bitbang_spi_set_mosi_set_sck(master, (val >> i) & 1, cpha); programmer_delay(master->half_period); - bitbang_spi_set_sck(master, 1); + bitbang_spi_set_sck(master, !cpha); programmer_delay(master->half_period); } } @@ -98,13 +109,17 @@ */ bitbang_spi_request_bus(master); bitbang_spi_set_cs(master, 0); + if (cpha) + programmer_delay(master->half_period); + for (i = 0; i < writecnt; i++) bitbang_spi_write_byte(master, writearr[i]); for (i = 0; i < readcnt; i++) readarr[i] = bitbang_spi_read_byte(master); bitbang_spi_set_sck(master, 0); - programmer_delay(master->half_period); + if (!cpha) + programmer_delay(master->half_period); bitbang_spi_set_cs(master, 1); programmer_delay(master->half_period); /* FIXME: Run bitbang_spi_release_bus here or in programmer init? */ @@ -132,6 +147,27 @@ } #endif +static int parse_spi_mode(int *polarity, int *phase) +{ + char *mode = extract_programmer_param("mode"); + if (!mode) + return 0; + + if (strlen(mode)) { + char *endptr; + int v = strtol(mode, &endptr, 0); + if (mode == endptr || v > 3 || v < 0) { + msg_perr("Invalid bitbang SPI mode, valid values are 0..3\n"); + free(mode); + return -1; + } + *polarity = (v >> 1) & 1; + *phase = (v >> 0) & 1; + } + free(mode); + return 0; +} + int register_spi_bitbang_master(const struct bitbang_spi_master *master) { struct spi_master mst = spi_master_bitbang; @@ -145,6 +181,9 @@ return ERROR_FLASHROM_BUG; } + if (parse_spi_mode(&cpol, &cpha)) + return ERROR_FATAL; + mst.data = master; register_spi_master(&mst); -- To view, visit https://review.coreboot.org/c/flashrom/+/49271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I415a528c013f1a523e883d812b6890be39bfcc7b Gerrit-Change-Number: 49271 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: bitbang_spi.c: Do not set MOSI during initialization
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/49270 ) Change subject: bitbang_spi.c: Do not set MOSI during initialization ...................................................................... bitbang_spi.c: Do not set MOSI during initialization With CS# deasserted, the value is ignored. Ensuring SCK is in the idle state is enough here. This is necessary because setting MOSI will assert SCK with CPHA=1, which is implemented in subsequent commits. Change-Id: I925d0ae55ae006dfcc6e7fb90364235526c576ef Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M bitbang_spi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/70/49270/1 diff --git a/bitbang_spi.c b/bitbang_spi.c index dfcf503..00c631f 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -151,7 +151,7 @@ /* Only mess with the bus if we're sure nobody else uses it. */ bitbang_spi_request_bus(master); bitbang_spi_set_cs(master, 1); - bitbang_spi_set_mosi_set_sck(master, 0, 0); + bitbang_spi_set_sck(master, 0); /* FIXME: Release SPI bus here and request it again for each command or * don't release it now and only release it on programmer shutdown? */ -- To view, visit https://review.coreboot.org/c/flashrom/+/49270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I925d0ae55ae006dfcc6e7fb90364235526c576ef Gerrit-Change-Number: 49270 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: bitbang_spi: Refactor `set_sck_set_mosi`
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/49269 ) Change subject: bitbang_spi: Refactor `set_sck_set_mosi` ...................................................................... bitbang_spi: Refactor `set_sck_set_mosi` Set the state of MOSI before changing SCK. This makes no difference for programmers that set both signals at once, but may improve reliability for those that do not, because MOSI now has more time to stabilize. Change-Id: Ia84d32965e56ca563062893ebbefbbea5c35814c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M bitbang_spi.c M developerbox_spi.c M mcp6x_spi.c M nicintel_spi.c M ogp_spi.c M pony_spi.c M programmer.h M rayer_spi.c 8 files changed, 23 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/69/49269/1 diff --git a/bitbang_spi.c b/bitbang_spi.c index 1b0692c..dfcf503 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -44,9 +44,9 @@ master->release_bus(); } -static void bitbang_spi_set_sck_set_mosi(const struct bitbang_spi_master * const master, int sck, int mosi) +static void bitbang_spi_set_mosi_set_sck(const struct bitbang_spi_master * const master, int mosi, int sck) { - master->set_sck_set_mosi(sck, mosi); + master->set_mosi_set_sck(mosi, sck); } static int bitbang_spi_set_sck_get_miso(const struct bitbang_spi_master * const master, int sck) @@ -61,7 +61,7 @@ for (i = 7; i >= 0; i--) { if (i == 0) - bitbang_spi_set_sck_set_mosi(master, 0, 0); + bitbang_spi_set_mosi_set_sck(master, 0, 0); else bitbang_spi_set_sck(master, 0); programmer_delay(master->half_period); @@ -77,7 +77,7 @@ int i; for (i = 7; i >= 0; i--) { - bitbang_spi_set_sck_set_mosi(master, 0, (val >> i) & 1); + bitbang_spi_set_mosi_set_sck(master, (val >> i) & 1, 0); programmer_delay(master->half_period); bitbang_spi_set_sck(master, 1); programmer_delay(master->half_period); @@ -137,7 +137,7 @@ struct spi_master mst = spi_master_bitbang; /* If someone forgot to initialize a bitbang function, we catch it here. */ if (!master || !master->set_cs || - !master->set_sck || !master->set_sck_set_mosi || !master->set_sck_get_miso || + !master->set_sck || !master->set_mosi_set_sck || !master->set_sck_get_miso || (master->request_bus && !master->release_bus) || (!master->request_bus && master->release_bus)) { msg_perr("Incomplete SPI bitbang master setting!\n" @@ -151,7 +151,7 @@ /* Only mess with the bus if we're sure nobody else uses it. */ bitbang_spi_request_bus(master); bitbang_spi_set_cs(master, 1); - bitbang_spi_set_sck_set_mosi(master, 0, 0); + bitbang_spi_set_mosi_set_sck(master, 0, 0); /* FIXME: Release SPI bus here and request it again for each command or * don't release it now and only release it on programmer shutdown? */ diff --git a/developerbox_spi.c b/developerbox_spi.c index 7011c9a..0c33dfb 100644 --- a/developerbox_spi.c +++ b/developerbox_spi.c @@ -104,7 +104,7 @@ cp210x_gpio_set(val << DEVELOPERBOX_SPI_SCK, 1 << DEVELOPERBOX_SPI_SCK); } -static void cp210x_bitbang_set_sck_set_mosi(int sck, int mosi) +static void cp210x_bitbang_set_mosi_set_sck(int mosi, int sck) { cp210x_gpio_set(sck << DEVELOPERBOX_SPI_SCK | mosi << DEVELOPERBOX_SPI_MOSI, 1 << DEVELOPERBOX_SPI_SCK | 1 << DEVELOPERBOX_SPI_MOSI); @@ -119,7 +119,7 @@ static const struct bitbang_spi_master bitbang_spi_master_cp210x = { .set_cs = cp210x_bitbang_set_cs, .set_sck = cp210x_bitbang_set_sck, - .set_sck_set_mosi = cp210x_bitbang_set_sck_set_mosi, + .set_mosi_set_sck = cp210x_bitbang_set_mosi_set_sck, .set_sck_get_miso = cp210x_bitbang_set_sck_get_miso, }; diff --git a/mcp6x_spi.c b/mcp6x_spi.c index a0e51fc..c99174c 100644 --- a/mcp6x_spi.c +++ b/mcp6x_spi.c @@ -74,7 +74,7 @@ mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); } -static void mcp6x_bitbang_set_sck_set_mosi(int sck, int mosi) +static void mcp6x_bitbang_set_mosi_set_sck(int mosi, int sck) { mcp_gpiostate &= ~(1 << MCP6X_SPI_SCK); mcp_gpiostate &= ~(1 << MCP6X_SPI_MOSI); @@ -95,7 +95,7 @@ static const struct bitbang_spi_master bitbang_spi_master_mcp6x = { .set_cs = mcp6x_bitbang_set_cs, .set_sck = mcp6x_bitbang_set_sck, - .set_sck_set_mosi = mcp6x_bitbang_set_sck_set_mosi, + .set_mosi_set_sck = mcp6x_bitbang_set_mosi_set_sck, .set_sck_get_miso = mcp6x_bitbang_set_sck_get_miso, .request_bus = mcp6x_request_spibus, .release_bus = mcp6x_release_spibus, diff --git a/nicintel_spi.c b/nicintel_spi.c index f16c2cd..5c210cd 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -148,7 +148,7 @@ pci_mmio_writel(tmp, nicintel_spibar + FLA); } -static void nicintel_bitbang_set_sck_set_mosi(int sck, int mosi) +static void nicintel_bitbang_set_mosi_set_sck(int mosi, int sck) { uint32_t tmp; @@ -174,7 +174,7 @@ static const struct bitbang_spi_master bitbang_spi_master_nicintel = { .set_cs = nicintel_bitbang_set_cs, .set_sck = nicintel_bitbang_set_sck, - .set_sck_set_mosi = nicintel_bitbang_set_sck_set_mosi, + .set_mosi_set_sck = nicintel_bitbang_set_mosi_set_sck, .set_sck_get_miso = nicintel_bitbang_set_sck_get_miso, .request_bus = nicintel_request_spibus, .release_bus = nicintel_release_spibus, diff --git a/ogp_spi.c b/ogp_spi.c index c2a4d18..355d452 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -69,10 +69,10 @@ pci_mmio_writel(val, ogp_spibar + ogp_reg_sck); } -static void ogp_bitbang_set_sck_set_mosi(int sck, int mosi) +static void ogp_bitbang_set_mosi_set_sck(int mosi, int sck) { - ogp_bitbang_set_sck(sck); pci_mmio_writel(mosi, ogp_spibar + ogp_reg_siso); + ogp_bitbang_set_sck(sck); } static int ogp_bitbang_set_sck_get_miso(int sck) @@ -88,7 +88,7 @@ static const struct bitbang_spi_master bitbang_spi_master_ogp = { .set_cs = ogp_bitbang_set_cs, .set_sck = ogp_bitbang_set_sck, - .set_sck_set_mosi = ogp_bitbang_set_sck_set_mosi, + .set_mosi_set_sck = ogp_bitbang_set_mosi_set_sck, .set_sck_get_miso = ogp_bitbang_set_sck_get_miso, .request_bus = ogp_request_spibus, .release_bus = ogp_release_spibus, diff --git a/pony_spi.c b/pony_spi.c index 37d0f08..131ac28 100644 --- a/pony_spi.c +++ b/pony_spi.c @@ -72,14 +72,14 @@ sp_set_pin(PIN_RTS, val); } -static void pony_bitbang_set_sck_set_mosi(int sck, int mosi) +static void pony_bitbang_set_mosi_set_sck(int mosi, int sck) { - pony_bitbang_set_sck(sck); - if (pony_negate_mosi) mosi ^= 1; sp_set_pin(PIN_DTR, mosi); + + pony_bitbang_set_sck(sck); } static int pony_bitbang_set_sck_get_miso(int sck) @@ -97,7 +97,7 @@ static const struct bitbang_spi_master bitbang_spi_master_pony = { .set_cs = pony_bitbang_set_cs, .set_sck = pony_bitbang_set_sck, - .set_sck_set_mosi = pony_bitbang_set_sck_set_mosi, + .set_mosi_set_sck = pony_bitbang_set_mosi_set_sck, .set_sck_get_miso = pony_bitbang_set_sck_get_miso, .half_period = 0, }; @@ -197,7 +197,7 @@ * Detect if there is a compatible hardware programmer connected. */ pony_bitbang_set_cs(1); - pony_bitbang_set_sck_set_mosi(1, 1); + pony_bitbang_set_mosi_set_sck(1, 1); switch (type) { case TYPE_AJAWE: diff --git a/programmer.h b/programmer.h index 51e7e88..9c94694 100644 --- a/programmer.h +++ b/programmer.h @@ -184,7 +184,7 @@ /* Note that CS# is active low, so val=0 means the chip is active. */ void (*set_cs) (int val); void (*set_sck) (int val); - void (*set_sck_set_mosi) (int sck, int mosi); + void (*set_mosi_set_sck) (int mosi, int sck); int (*set_sck_get_miso) (int sck); void (*request_bus) (void); void (*release_bus) (void); diff --git a/rayer_spi.c b/rayer_spi.c index 1649f1b..c956a1b 100644 --- a/rayer_spi.c +++ b/rayer_spi.c @@ -140,7 +140,7 @@ OUTB(lpt_outbyte, lpt_iobase); } -static void rayer_bitbang_set_sck_set_mosi(int sck, int mosi) +static void rayer_bitbang_set_mosi_set_sck(int mosi, int sck) { lpt_outbyte &= ~(1 << pinout->sck_bit); lpt_outbyte &= ~(1 << pinout->mosi_bit); @@ -163,7 +163,7 @@ static const struct bitbang_spi_master bitbang_spi_master_rayer = { .set_cs = rayer_bitbang_set_cs, .set_sck = rayer_bitbang_set_sck, - .set_sck_set_mosi = rayer_bitbang_set_sck_set_mosi, + .set_mosi_set_sck = rayer_bitbang_set_mosi_set_sck, .set_sck_get_miso = rayer_bitbang_set_sck_get_miso, .half_period = 0, }; -- To view, visit https://review.coreboot.org/c/flashrom/+/49269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia84d32965e56ca563062893ebbefbbea5c35814c Gerrit-Change-Number: 49269 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: bitbang_spi: Drop `set_mosi` and `get_miso` operations
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/49268 ) Change subject: bitbang_spi: Drop `set_mosi` and `get_miso` operations ...................................................................... bitbang_spi: Drop `set_mosi` and `get_miso` operations The bitbang_spi code always sets SCK before doing either of these two operations. Make `set_sck_set_mosi` and `set_sck_get_miso` mandatory and implement them everywhere, and remove `set_mosi` and `get_miso`. Change-Id: Id6b1edb1e01330feffc5f1ed2ca2c2ebc4fb3b66 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M bitbang_spi.c M developerbox_spi.c M mcp6x_spi.c M nicintel_spi.c M ogp_spi.c M pony_spi.c M programmer.h M rayer_spi.c 8 files changed, 36 insertions(+), 90 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/68/49268/1 diff --git a/bitbang_spi.c b/bitbang_spi.c index c402119..1b0692c 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -46,22 +46,12 @@ static void bitbang_spi_set_sck_set_mosi(const struct bitbang_spi_master * const master, int sck, int mosi) { - if (master->set_sck_set_mosi) { - master->set_sck_set_mosi(sck, mosi); - return; - } - - master->set_sck(sck); - master->set_mosi(mosi); + master->set_sck_set_mosi(sck, mosi); } static int bitbang_spi_set_sck_get_miso(const struct bitbang_spi_master * const master, int sck) { - if (master->set_sck_get_miso) - return master->set_sck_get_miso(sck); - - master->set_sck(sck); - return master->get_miso(); + return master->set_sck_get_miso(sck); } static uint8_t bitbang_spi_read_byte(const struct bitbang_spi_master *master) @@ -147,7 +137,7 @@ struct spi_master mst = spi_master_bitbang; /* If someone forgot to initialize a bitbang function, we catch it here. */ if (!master || !master->set_cs || - !master->set_sck || !master->set_mosi || !master->get_miso || + !master->set_sck || !master->set_sck_set_mosi || !master->set_sck_get_miso || (master->request_bus && !master->release_bus) || (!master->request_bus && master->release_bus)) { msg_perr("Incomplete SPI bitbang master setting!\n" diff --git a/developerbox_spi.c b/developerbox_spi.c index 4ff2fb6..7011c9a 100644 --- a/developerbox_spi.c +++ b/developerbox_spi.c @@ -104,28 +104,23 @@ cp210x_gpio_set(val << DEVELOPERBOX_SPI_SCK, 1 << DEVELOPERBOX_SPI_SCK); } -static void cp210x_bitbang_set_mosi(int val) -{ - cp210x_gpio_set(val << DEVELOPERBOX_SPI_MOSI, 1 << DEVELOPERBOX_SPI_MOSI); -} - -static int cp210x_bitbang_get_miso(void) -{ - return !!(cp210x_gpio_get() & (1 << DEVELOPERBOX_SPI_MISO)); -} - static void cp210x_bitbang_set_sck_set_mosi(int sck, int mosi) { cp210x_gpio_set(sck << DEVELOPERBOX_SPI_SCK | mosi << DEVELOPERBOX_SPI_MOSI, 1 << DEVELOPERBOX_SPI_SCK | 1 << DEVELOPERBOX_SPI_MOSI); } +static int cp210x_bitbang_set_sck_get_miso(int sck) +{ + cp210x_bitbang_set_sck(sck); + return !!(cp210x_gpio_get() & (1 << DEVELOPERBOX_SPI_MISO)); +} + static const struct bitbang_spi_master bitbang_spi_master_cp210x = { .set_cs = cp210x_bitbang_set_cs, .set_sck = cp210x_bitbang_set_sck, - .set_mosi = cp210x_bitbang_set_mosi, - .get_miso = cp210x_bitbang_get_miso, .set_sck_set_mosi = cp210x_bitbang_set_sck_set_mosi, + .set_sck_get_miso = cp210x_bitbang_set_sck_get_miso, }; static int developerbox_spi_shutdown(void *data) diff --git a/mcp6x_spi.c b/mcp6x_spi.c index 4f82095..a0e51fc 100644 --- a/mcp6x_spi.c +++ b/mcp6x_spi.c @@ -74,19 +74,6 @@ mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); } -static void mcp6x_bitbang_set_mosi(int val) -{ - mcp_gpiostate &= ~(1 << MCP6X_SPI_MOSI); - mcp_gpiostate |= (val << MCP6X_SPI_MOSI); - mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); -} - -static int mcp6x_bitbang_get_miso(void) -{ - mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); - return (mcp_gpiostate >> MCP6X_SPI_MISO) & 0x1; -} - static void mcp6x_bitbang_set_sck_set_mosi(int sck, int mosi) { mcp_gpiostate &= ~(1 << MCP6X_SPI_SCK); @@ -108,8 +95,6 @@ static const struct bitbang_spi_master bitbang_spi_master_mcp6x = { .set_cs = mcp6x_bitbang_set_cs, .set_sck = mcp6x_bitbang_set_sck, - .set_mosi = mcp6x_bitbang_set_mosi, - .get_miso = mcp6x_bitbang_get_miso, .set_sck_set_mosi = mcp6x_bitbang_set_sck_set_mosi, .set_sck_get_miso = mcp6x_bitbang_set_sck_get_miso, .request_bus = mcp6x_request_spibus, diff --git a/nicintel_spi.c b/nicintel_spi.c index c068e75..f16c2cd 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -148,25 +148,6 @@ pci_mmio_writel(tmp, nicintel_spibar + FLA); } -static void nicintel_bitbang_set_mosi(int val) -{ - uint32_t tmp; - - tmp = pci_mmio_readl(nicintel_spibar + FLA); - tmp &= ~BIT(FL_SI); - tmp |= (val << FL_SI); - pci_mmio_writel(tmp, nicintel_spibar + FLA); -} - -static int nicintel_bitbang_get_miso(void) -{ - uint32_t tmp; - - tmp = pci_mmio_readl(nicintel_spibar + FLA); - tmp = (tmp >> FL_SO) & 0x1; - return tmp; -} - static void nicintel_bitbang_set_sck_set_mosi(int sck, int mosi) { uint32_t tmp; @@ -193,8 +174,6 @@ static const struct bitbang_spi_master bitbang_spi_master_nicintel = { .set_cs = nicintel_bitbang_set_cs, .set_sck = nicintel_bitbang_set_sck, - .set_mosi = nicintel_bitbang_set_mosi, - .get_miso = nicintel_bitbang_get_miso, .set_sck_set_mosi = nicintel_bitbang_set_sck_set_mosi, .set_sck_get_miso = nicintel_bitbang_set_sck_get_miso, .request_bus = nicintel_request_spibus, diff --git a/ogp_spi.c b/ogp_spi.c index e603edb..c2a4d18 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -69,13 +69,16 @@ pci_mmio_writel(val, ogp_spibar + ogp_reg_sck); } -static void ogp_bitbang_set_mosi(int val) +static void ogp_bitbang_set_sck_set_mosi(int sck, int mosi) { - pci_mmio_writel(val, ogp_spibar + ogp_reg_siso); + ogp_bitbang_set_sck(sck); + pci_mmio_writel(mosi, ogp_spibar + ogp_reg_siso); } -static int ogp_bitbang_get_miso(void) +static int ogp_bitbang_set_sck_get_miso(int sck) { + ogp_bitbang_set_sck(sck); + uint32_t tmp; tmp = pci_mmio_readl(ogp_spibar + ogp_reg_siso); @@ -85,8 +88,8 @@ static const struct bitbang_spi_master bitbang_spi_master_ogp = { .set_cs = ogp_bitbang_set_cs, .set_sck = ogp_bitbang_set_sck, - .set_mosi = ogp_bitbang_set_mosi, - .get_miso = ogp_bitbang_get_miso, + .set_sck_set_mosi = ogp_bitbang_set_sck_set_mosi, + .set_sck_get_miso = ogp_bitbang_set_sck_get_miso, .request_bus = ogp_request_spibus, .release_bus = ogp_release_spibus, .half_period = 0, diff --git a/pony_spi.c b/pony_spi.c index ed9d326..37d0f08 100644 --- a/pony_spi.c +++ b/pony_spi.c @@ -72,16 +72,20 @@ sp_set_pin(PIN_RTS, val); } -static void pony_bitbang_set_mosi(int val) +static void pony_bitbang_set_sck_set_mosi(int sck, int mosi) { - if (pony_negate_mosi) - val ^= 1; + pony_bitbang_set_sck(sck); - sp_set_pin(PIN_DTR, val); + if (pony_negate_mosi) + mosi ^= 1; + + sp_set_pin(PIN_DTR, mosi); } -static int pony_bitbang_get_miso(void) +static int pony_bitbang_set_sck_get_miso(int sck) { + pony_bitbang_set_sck(sck); + int tmp = sp_get_pin(PIN_CTS); if (pony_negate_miso) @@ -93,8 +97,8 @@ static const struct bitbang_spi_master bitbang_spi_master_pony = { .set_cs = pony_bitbang_set_cs, .set_sck = pony_bitbang_set_sck, - .set_mosi = pony_bitbang_set_mosi, - .get_miso = pony_bitbang_get_miso, + .set_sck_set_mosi = pony_bitbang_set_sck_set_mosi, + .set_sck_get_miso = pony_bitbang_set_sck_get_miso, .half_period = 0, }; @@ -193,8 +197,7 @@ * Detect if there is a compatible hardware programmer connected. */ pony_bitbang_set_cs(1); - pony_bitbang_set_sck(1); - pony_bitbang_set_mosi(1); + pony_bitbang_set_sck_set_mosi(1, 1); switch (type) { case TYPE_AJAWE: diff --git a/programmer.h b/programmer.h index d66d239..51e7e88 100644 --- a/programmer.h +++ b/programmer.h @@ -184,13 +184,10 @@ /* Note that CS# is active low, so val=0 means the chip is active. */ void (*set_cs) (int val); void (*set_sck) (int val); - void (*set_mosi) (int val); - int (*get_miso) (void); - void (*request_bus) (void); - void (*release_bus) (void); - /* optional functions to optimize xfers */ void (*set_sck_set_mosi) (int sck, int mosi); int (*set_sck_get_miso) (int sck); + void (*request_bus) (void); + void (*release_bus) (void); /* Length of half a clock period in usecs. */ unsigned int half_period; }; diff --git a/rayer_spi.c b/rayer_spi.c index 8c7f53e..1649f1b 100644 --- a/rayer_spi.c +++ b/rayer_spi.c @@ -140,13 +140,6 @@ OUTB(lpt_outbyte, lpt_iobase); } -static void rayer_bitbang_set_mosi(int val) -{ - lpt_outbyte &= ~(1 << pinout->mosi_bit); - lpt_outbyte |= (val << pinout->mosi_bit); - OUTB(lpt_outbyte, lpt_iobase); -} - static void rayer_bitbang_set_sck_set_mosi(int sck, int mosi) { lpt_outbyte &= ~(1 << pinout->sck_bit); @@ -156,8 +149,10 @@ OUTB(lpt_outbyte, lpt_iobase); } -static int rayer_bitbang_get_miso(void) +static int rayer_bitbang_set_sck_get_miso(int sck) { + rayer_bitbang_set_sck(sck); + uint8_t tmp; tmp = INB(lpt_iobase + 1) ^ 0x80; // bit.7 inverted @@ -168,9 +163,8 @@ static const struct bitbang_spi_master bitbang_spi_master_rayer = { .set_cs = rayer_bitbang_set_cs, .set_sck = rayer_bitbang_set_sck, - .set_mosi = rayer_bitbang_set_mosi, .set_sck_set_mosi = rayer_bitbang_set_sck_set_mosi, - .get_miso = rayer_bitbang_get_miso, + .set_sck_get_miso = rayer_bitbang_set_sck_get_miso, .half_period = 0, }; -- To view, visit https://review.coreboot.org/c/flashrom/+/49268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id6b1edb1e01330feffc5f1ed2ca2c2ebc4fb3b66 Gerrit-Change-Number: 49268 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: nicintel_spi.c: Implement `set_sck_set_mosi` and `set_sck_get_miso`
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/49267 ) Change subject: nicintel_spi.c: Implement `set_sck_set_mosi` and `set_sck_get_miso` ...................................................................... nicintel_spi.c: Implement `set_sck_set_mosi` and `set_sck_get_miso` Change-Id: I52a0ae5ff331ee2ed41652eb5c2ed7ebe7253d74 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M nicintel_spi.c 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/67/49267/1 diff --git a/nicintel_spi.c b/nicintel_spi.c index 1173ef7..c068e75 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -167,11 +167,36 @@ return tmp; } +static void nicintel_bitbang_set_sck_set_mosi(int sck, int mosi) +{ + uint32_t tmp; + + tmp = pci_mmio_readl(nicintel_spibar + FLA); + tmp &= ~BIT(FL_SCK); + tmp &= ~BIT(FL_SI); + tmp |= (sck << FL_SCK); + tmp |= (mosi << FL_SI); + pci_mmio_writel(tmp, nicintel_spibar + FLA); +} + +static int nicintel_bitbang_set_sck_get_miso(int sck) +{ + uint32_t tmp; + + tmp = pci_mmio_readl(nicintel_spibar + FLA); + tmp &= ~BIT(FL_SCK); + tmp |= (sck << FL_SCK); + pci_mmio_writel(tmp, nicintel_spibar + FLA); + return (tmp >> FL_SO) & 0x1; +} + static const struct bitbang_spi_master bitbang_spi_master_nicintel = { .set_cs = nicintel_bitbang_set_cs, .set_sck = nicintel_bitbang_set_sck, .set_mosi = nicintel_bitbang_set_mosi, .get_miso = nicintel_bitbang_get_miso, + .set_sck_set_mosi = nicintel_bitbang_set_sck_set_mosi, + .set_sck_get_miso = nicintel_bitbang_set_sck_get_miso, .request_bus = nicintel_request_spibus, .release_bus = nicintel_release_spibus, .half_period = 1, -- To view, visit https://review.coreboot.org/c/flashrom/+/49267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I52a0ae5ff331ee2ed41652eb5c2ed7ebe7253d74 Gerrit-Change-Number: 49267 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: mcp6x_spi.c: Implement `set_sck_set_mosi` and `set_sck_get_miso`
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/49266 ) Change subject: mcp6x_spi.c: Implement `set_sck_set_mosi` and `set_sck_get_miso` ...................................................................... mcp6x_spi.c: Implement `set_sck_set_mosi` and `set_sck_get_miso` Change-Id: Ie86cc9d4df6c7f0609c30ff00d6f2d77fbb8b836 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M mcp6x_spi.c 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/66/49266/1 diff --git a/mcp6x_spi.c b/mcp6x_spi.c index b53d07b..4f82095 100644 --- a/mcp6x_spi.c +++ b/mcp6x_spi.c @@ -87,11 +87,31 @@ return (mcp_gpiostate >> MCP6X_SPI_MISO) & 0x1; } +static void mcp6x_bitbang_set_sck_set_mosi(int sck, int mosi) +{ + mcp_gpiostate &= ~(1 << MCP6X_SPI_SCK); + mcp_gpiostate &= ~(1 << MCP6X_SPI_MOSI); + mcp_gpiostate |= (sck << MCP6X_SPI_SCK); + mcp_gpiostate |= (mosi << MCP6X_SPI_MOSI); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); +} + +static int mcp6x_bitbang_set_sck_get_miso(int sck) +{ + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); + mcp_gpiostate &= ~(1 << MCP6X_SPI_SCK); + mcp_gpiostate |= (sck << MCP6X_SPI_SCK); + mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); + return (mcp_gpiostate >> MCP6X_SPI_MISO) & 0x1; +} + static const struct bitbang_spi_master bitbang_spi_master_mcp6x = { .set_cs = mcp6x_bitbang_set_cs, .set_sck = mcp6x_bitbang_set_sck, .set_mosi = mcp6x_bitbang_set_mosi, .get_miso = mcp6x_bitbang_get_miso, + .set_sck_set_mosi = mcp6x_bitbang_set_sck_set_mosi, + .set_sck_get_miso = mcp6x_bitbang_set_sck_get_miso, .request_bus = mcp6x_request_spibus, .release_bus = mcp6x_release_spibus, .half_period = 0, -- To view, visit https://review.coreboot.org/c/flashrom/+/49266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie86cc9d4df6c7f0609c30ff00d6f2d77fbb8b836 Gerrit-Change-Number: 49266 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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