Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/35479 )
Change subject: flashchips.c: Take GD25LQ40 from downstream
......................................................................
flashchips.c: Take GD25LQ40 from downstream
Take definition of GD25LQ40 from ChromiumOS repository. This chip was
added in `commit 59543cd1` by dnschneid(a)chromium.org on 2016-04-27. The
commit message notes that some testing had been done, even thought the
.tested attribute was left as UNTESTED.
Signed-off-by: Alan Green <avg(a)google.com>
Change-Id: I978745b38536cda807adf07af4e4d093d0d93ad1
---
M flashchips.c
1 file changed, 2 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/35479/1
diff --git a/flashchips.c b/flashchips.c
index 5c797fd..ac07fa8 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -6009,7 +6009,7 @@
.total_size = 512,
.page_size = 256,
/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */
- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
+ .feature_bits = FEATURE_WRSR_WREN,
.tested = TEST_UNTESTED,
.probe = probe_spi_rdid,
.probe_timing = TIMING_ZERO,
@@ -6032,8 +6032,7 @@
.block_erase = spi_block_erase_c7,
}
},
- .printlock = spi_prettyprint_status_register_bp4_srwd,
- .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */
+ .unlock = spi_disable_blockprotect,
.write = spi_chip_write_256,
.read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
.voltage = {1695, 1950},
--
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I978745b38536cda807adf07af4e4d093d0d93ad1
Gerrit-Change-Number: 35479
Gerrit-PatchSet: 1
Gerrit-Owner: Alan Green <avg(a)google.com>
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Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/49001 )
Change subject: ichspi: print transaction error in debug mode
......................................................................
ichspi: print transaction error in debug mode
When "--fmap" option is used, flashrom does binary search in flash for
fmap. When it reads flash region that is locked, transaction error happens.
Print transaction error in debug mode, so that following message:
Transaction error between offset 0x02cb4000 and 0x02cb4007 (= 0x02cb4000 + 7)!
shows up only when "-V" is specified.
Change-Id: Iebed1ae7f15b7f06b90a0b5947b953f7f0e1567d
Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com>
---
M ichspi.c
1 file changed, 7 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/01/49001/1
diff --git a/ichspi.c b/ichspi.c
index 4209d60..6dde7b2 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1311,11 +1311,17 @@
if (hsfs & HSFS_FCERR) {
addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask;
- msg_perr("Transaction error between offset 0x%08x and "
+
+ /*
+ * If the partition is locked, this transaction error happens.
+ * Print in verbose mode to avoid excessive messages.
+ */
+ msg_cdbg("Transaction error between offset 0x%08x and "
"0x%08x (= 0x%08x + %d)!\n",
addr, addr + len - 1, addr, len - 1);
prettyprint_ich9_reg_hsfs(hsfs, ich_gen);
prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC), ich_gen);
+
return 1;
}
return 0;
--
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Gerrit-Change-Id: Iebed1ae7f15b7f06b90a0b5947b953f7f0e1567d
Gerrit-Change-Number: 49001
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Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com>
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/48949 )
Change subject: flashchips.c: Add support for XMC new SPI flash types
......................................................................
Patch Set 6: Code-Review+2
(1 comment)
https://review.coreboot.org/c/flashrom/+/48949/3//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/flashrom/+/48949/3//COMMIT_MSG@16
PS3, Line 16: TEST=test
> Was a test actually performed? […]
I edited the commit message to fix it up for you. Thanks for contributing, it would be great to see more of your chips added as well.
--
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Gerrit-Change-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969
Gerrit-Change-Number: 48949
Gerrit-PatchSet: 6
Gerrit-Owner: luke <sixuerain(a)qq.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Carl-Daniel Hailfinger <hailfinger(a)gmail.com>
Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com>
Gerrit-Reviewer: Uwe Hermann <uwe(a)hermann-uwe.de>
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Gerrit-Comment-Date: Fri, 01 Jan 2021 03:07:57 +0000
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Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-MessageType: comment
Edward O'Callaghan has uploaded a new patch set (#6) to the change originally created by luke. ( https://review.coreboot.org/c/flashrom/+/48949 )
Change subject: flashchips.c: Add support for XMC new SPI flash types
......................................................................
flashchips.c: Add support for XMC new SPI flash types
Adds initial support for the follow SPI flash chips:
XM25QU64C
XM25QU128C
XM25QU256C
XM25QH64C
XM25QH128C
XM25QH256C
BUG=none
TEST=builds
Signed-off-by: Luke He <sixuerain(a)qq.com>
Change-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969
---
M flashchips.c
M flashchips.h
2 files changed, 245 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/49/48949/6
--
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Gerrit-Change-Number: 48949
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Gerrit-Owner: luke <sixuerain(a)qq.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Carl-Daniel Hailfinger <hailfinger(a)gmail.com>
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