flashrom-gerrit January 2021

flashrom-gerrit@flashrom.org

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Change in flashrom[master]: flashchips.c: Take GD25LQ40 from downstream
by Alan Green (Code Review) 05 Jan '21

05 Jan '21

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/35479 ) Change subject: flashchips.c: Take GD25LQ40 from downstream ...................................................................... flashchips.c: Take GD25LQ40 from downstream Take definition of GD25LQ40 from ChromiumOS repository. This chip was added in `commit 59543cd1` by dnschneid(a)chromium.org on 2016-04-27. The commit message notes that some testing had been done, even thought the .tested attribute was left as UNTESTED. Signed-off-by: Alan Green <avg(a)google.com> Change-Id: I978745b38536cda807adf07af4e4d093d0d93ad1 --- M flashchips.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/35479/1 diff --git a/flashchips.c b/flashchips.c index 5c797fd..ac07fa8 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6009,7 +6009,7 @@ .total_size = 512, .page_size = 256, /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -6032,8 +6032,7 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_bp4_srwd, - .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1695, 1950}, -- To view, visit https://review.coreboot.org/c/flashrom/+/35479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I978745b38536cda807adf07af4e4d093d0d93ad1 Gerrit-Change-Number: 35479 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips.c: Add support for XMC new SPI flash types
by Edward O'Callaghan (Code Review) 01 Jan '21

01 Jan '21

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/48949 ) Change subject: flashchips.c: Add support for XMC new SPI flash types ...................................................................... flashchips.c: Add support for XMC new SPI flash types Adds initial support for the follow SPI flash chips: XM25QU64C XM25QU128C XM25QU256C XM25QH64C XM25QH128C XM25QH256C BUG=none TEST=builds Signed-off-by: Luke He <sixuerain(a)qq.com> Change-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969 Reviewed-on: https://review.coreboot.org/c/flashrom/+/48949 Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M flashchips.c M flashchips.h 2 files changed, 245 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index c4a1e6f..7590dff 100644 --- a/flashchips.c +++ b/flashchips.c @@ -18993,6 +18993,244 @@ }, { + .vendor = "XMC", + .name = "XM25QH64C", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QH64C, + .total_size = 8192, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "XMC", + .name = "XM25QU64C", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QU64C, + .total_size = 8192, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "XMC", + .name = "XM25QH128C", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QH128C, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "XMC", + .name = "XM25QU128C", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QU128C, + .total_size = 16384, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "XMC", + .name = "XM25QH256C", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QH256C, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN + | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "XMC", + .name = "XM25QU256C", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QU256C, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN + | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { .vendor = "Zetta Device", .name = "ZD25D20", .bustype = BUS_SPI, diff --git a/flashchips.h b/flashchips.h index 394eb30..a85fa6a 100644 --- a/flashchips.h +++ b/flashchips.h @@ -792,7 +792,7 @@ * ST25P chips are SPI, first byte of device ID is memory type, second * byte of device ID is related to log(bitsize) at least for some chips. */ -#define ST_ID 0x20 /* ST / SGS/Thomson / Numonyx (later acquired by Micron) */ +#define ST_ID 0x20 /* ST / SGS/Thomson / Numonyx / XMC(later acquired by Micron) */ #define ST_M25P05A 0x2010 #define ST_M25P05_RES 0x05 #define ST_M25P10A 0x2011 @@ -811,6 +811,12 @@ #define ST_M45PE40 0x4013 #define ST_M45PE80 0x4014 #define ST_M45PE16 0x4015 +#define XMC_XM25QH64C 0x4017 +#define XMC_XM25QU64C 0x4117 +#define XMC_XM25QH128C 0x4018 +#define XMC_XM25QU128C 0x4118 +#define XMC_XM25QH256C 0x4019 +#define XMC_XM25QU256C 0x4119 #define ST_M25PX80 0x7114 #define ST_M25PX16 0x7115 #define ST_M25PX32 0x7116 -- To view, visit https://review.coreboot.org/c/flashrom/+/48949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969 Gerrit-Change-Number: 48949 Gerrit-PatchSet: 7 Gerrit-Owner: luke <sixuerain(a)qq.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Carl-Daniel Hailfinger <hailfinger(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Uwe Hermann <uwe(a)hermann-uwe.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in flashrom[master]: realtek_mst_i2c_spi.c: Consolidate shifts to the one fn
by Edward O'Callaghan (Code Review) 01 Jan '21

01 Jan '21

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48975 ) Change subject: realtek_mst_i2c_spi.c: Consolidate shifts to the one fn ...................................................................... realtek_mst_i2c_spi.c: Consolidate shifts to the one fn To avoid further incorrect mappings ensure all the shifting happens within realtek_mst_i2c_spi_map_page() itself. BUG=none BRANCH=none TEST=builds Change-Id: I96c595b1abae044347fb0c2c91b891a60dd3675e Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Suggested-by: Angel Pons <th3fanbus(a)gmail.com> --- M realtek_mst_i2c_spi.c 1 file changed, 8 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/75/48975/1 diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 3e84b23..418e23a 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -289,9 +289,14 @@ return ret; } -static int realtek_mst_i2c_spi_map_page(int fd, uint8_t block_idx, uint8_t page_idx, uint8_t byte_idx) +static int realtek_mst_i2c_spi_map_page(int fd, uint32_t addr) { int ret = 0; + + uint8_t block_idx = (addr >> 16) & 0xff; + uint8_t page_idx = (addr >> 8) & 0xff; + uint8_t byte_idx = addr & 0xff; + ret |= realtek_mst_i2c_spi_write_register(fd, MAP_PAGE_BYTE2, block_idx); ret |= realtek_mst_i2c_spi_write_register(fd, MAP_PAGE_BYTE1, page_idx); ret |= realtek_mst_i2c_spi_write_register(fd, MAP_PAGE_BYTE0, byte_idx); @@ -330,10 +335,7 @@ start--; ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, 0x46); // ** ret |= realtek_mst_i2c_spi_write_register(fd, 0x61, OPCODE_READ); - uint8_t block_idx = (start >> 16) & 0xff; - uint8_t page_idx = (start >> 8) & 0xff; - uint8_t byte_idx = start & 0xff; - ret |= realtek_mst_i2c_spi_map_page(fd, block_idx, page_idx, byte_idx); + ret |= realtek_mst_i2c_spi_map_page(fd, start); ret |= realtek_mst_i2c_spi_write_register(fd, 0x6a, 0x03); ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, 0x47); // ** if (ret) @@ -384,10 +386,7 @@ uint16_t page_len = min(len - i, PAGE_SIZE); if (len - i < PAGE_SIZE) ret |= realtek_mst_i2c_spi_write_register(fd, 0x71, page_len-1); - uint8_t block_idx = ((start + i) >> 16) & 0xff; - uint8_t page_idx = ((start + i) >> 8) & 0xff; - uint8_t byte_idx = (start + i) & 0xff; - ret |= realtek_mst_i2c_spi_map_page(fd, block_idx, page_idx, byte_idx); + ret |= realtek_mst_i2c_spi_map_page(fd, (start + i)); if (ret) break; -- To view, visit https://review.coreboot.org/c/flashrom/+/48975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I96c595b1abae044347fb0c2c91b891a60dd3675e Gerrit-Change-Number: 48975 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 6

Change in flashrom[master]: realtek_mst_i2c_spi.c: Don't depend on int overflows
by Edward O'Callaghan (Code Review) 01 Jan '21

01 Jan '21

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48974 ) Change subject: realtek_mst_i2c_spi.c: Don't depend on int overflows ...................................................................... realtek_mst_i2c_spi.c: Don't depend on int overflows Be explicit to mask the first byte after the shifts as highlighted by Angel Pos. BUG=none BRANCH=none TEST=builds Change-Id: I7d1215678094d709e79b8f8c96aa3810586cd72e Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Spotted-by: Angel Pons <th3fanbus(a)gmail.com> --- M realtek_mst_i2c_spi.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/74/48974/1 diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index dabec70..3e84b23 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -330,9 +330,9 @@ start--; ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, 0x46); // ** ret |= realtek_mst_i2c_spi_write_register(fd, 0x61, OPCODE_READ); - uint8_t block_idx = start >> 16; - uint8_t page_idx = start >> 8; - uint8_t byte_idx = start; + uint8_t block_idx = (start >> 16) & 0xff; + uint8_t page_idx = (start >> 8) & 0xff; + uint8_t byte_idx = start & 0xff; ret |= realtek_mst_i2c_spi_map_page(fd, block_idx, page_idx, byte_idx); ret |= realtek_mst_i2c_spi_write_register(fd, 0x6a, 0x03); ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, 0x47); // ** @@ -384,9 +384,9 @@ uint16_t page_len = min(len - i, PAGE_SIZE); if (len - i < PAGE_SIZE) ret |= realtek_mst_i2c_spi_write_register(fd, 0x71, page_len-1); - uint8_t block_idx = (start + i) >> 16; - uint8_t page_idx = (start + i) >> 8; - uint8_t byte_idx = start + i; + uint8_t block_idx = ((start + i) >> 16) & 0xff; + uint8_t page_idx = ((start + i) >> 8) & 0xff; + uint8_t byte_idx = (start + i) & 0xff; ret |= realtek_mst_i2c_spi_map_page(fd, block_idx, page_idx, byte_idx); if (ret) break; -- To view, visit https://review.coreboot.org/c/flashrom/+/48974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7d1215678094d709e79b8f8c96aa3810586cd72e Gerrit-Change-Number: 48974 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi: print transaction error in debug mode
by Jonathan Zhang (Code Review) 31 Dec '20

31 Dec '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/49001 ) Change subject: ichspi: print transaction error in debug mode ...................................................................... ichspi: print transaction error in debug mode When "--fmap" option is used, flashrom does binary search in flash for fmap. When it reads flash region that is locked, transaction error happens. Print transaction error in debug mode, so that following message: Transaction error between offset 0x02cb4000 and 0x02cb4007 (= 0x02cb4000 + 7)! shows up only when "-V" is specified. Change-Id: Iebed1ae7f15b7f06b90a0b5947b953f7f0e1567d Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> --- M ichspi.c 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/01/49001/1 diff --git a/ichspi.c b/ichspi.c index 4209d60..6dde7b2 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1311,11 +1311,17 @@ if (hsfs & HSFS_FCERR) { addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask; - msg_perr("Transaction error between offset 0x%08x and " + + /* + * If the partition is locked, this transaction error happens. + * Print in verbose mode to avoid excessive messages. + */ + msg_cdbg("Transaction error between offset 0x%08x and " "0x%08x (= 0x%08x + %d)!\n", addr, addr + len - 1, addr, len - 1); prettyprint_ich9_reg_hsfs(hsfs, ich_gen); prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC), ich_gen); + return 1; } return 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/49001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iebed1ae7f15b7f06b90a0b5947b953f7f0e1567d Gerrit-Change-Number: 49001 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips.c: Add support for XMC new SPI flash types
by Edward O'Callaghan (Code Review) 31 Dec '20

31 Dec '20

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/48949 ) Change subject: flashchips.c: Add support for XMC new SPI flash types ...................................................................... Patch Set 6: Code-Review+2 (1 comment) https://review.coreboot.org/c/flashrom/+/48949/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/flashrom/+/48949/3//COMMIT_MSG@16 PS3, Line 16: TEST=test > Was a test actually performed? […] I edited the commit message to fix it up for you. Thanks for contributing, it would be great to see more of your chips added as well. -- To view, visit https://review.coreboot.org/c/flashrom/+/48949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969 Gerrit-Change-Number: 48949 Gerrit-PatchSet: 6 Gerrit-Owner: luke <sixuerain(a)qq.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Carl-Daniel Hailfinger <hailfinger(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Uwe Hermann <uwe(a)hermann-uwe.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Jan 2021 03:07:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in flashrom[master]: flashchips.c: Add support for XMC new SPI flash types
by Edward O'Callaghan (Code Review) 31 Dec '20

31 Dec '20

Edward O'Callaghan has uploaded a new patch set (#6) to the change originally created by luke. ( https://review.coreboot.org/c/flashrom/+/48949 ) Change subject: flashchips.c: Add support for XMC new SPI flash types ...................................................................... flashchips.c: Add support for XMC new SPI flash types Adds initial support for the follow SPI flash chips: XM25QU64C XM25QU128C XM25QU256C XM25QH64C XM25QH128C XM25QH256C BUG=none TEST=builds Signed-off-by: Luke He <sixuerain(a)qq.com> Change-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969 --- M flashchips.c M flashchips.h 2 files changed, 245 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/49/48949/6 -- To view, visit https://review.coreboot.org/c/flashrom/+/48949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969 Gerrit-Change-Number: 48949 Gerrit-PatchSet: 6 Gerrit-Owner: luke <sixuerain(a)qq.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Carl-Daniel Hailfinger <hailfinger(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Uwe Hermann <uwe(a)hermann-uwe.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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flashrom-gerrit January 2021