January 2021 - flashrom-gerrit

Change in flashrom[master]: bitbang-spi.c: support clock polarity and phase
by Edward O'Callaghan (Code Review) 09 Jan '21

09 Jan '21

Attention is currently required from: Xiang Wang, Stefan Reinauer, Angel Pons. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/49255 ) Change subject: bitbang-spi.c: support clock polarity and phase ...................................................................... Patch Set 1: Code-Review-1 (2 comments) Patchset: PS1: Too much going on in one patch with no commit msg body explaining anything. I think on a quick inspection there is at least two patches here, one for adding the mode and the other where you combine RW primitives. File bitbang_spi.c: https://review.coreboot.org/c/flashrom/+/49255/comment/07d5e9bf_d0880ff5 PS1, Line 78: bitbang_spi_xfer( this is its own patch. -- To view, visit https://review.coreboot.org/c/flashrom/+/49255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I04c1dfe132d756119229b27c3cd611d1be1abc8d Gerrit-Change-Number: 49255 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shawn C <citypw(a)hardenedlinux.org> Gerrit-Attention: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 09 Jan 2021 10:17:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: sysfsgpio.c implement spi interface via linux sysfs
by Xiang Wang (Code Review) 09 Jan '21

09 Jan '21

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/49254 ) Change subject: sysfsgpio.c implement spi interface via linux sysfs ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I have tested it on my raspberry pi zero, it works, but the speed is very slow. It takes about 30 minutes to read W25Q128.V -- To view, visit https://review.coreboot.org/c/flashrom/+/49254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1bc47ef8011bba560326b501a80869340bb9f733 Gerrit-Change-Number: 49254 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shawn C <citypw(a)hardenedlinux.org> Gerrit-Comment-Date: Sat, 09 Jan 2021 03:38:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: comment

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Change in flashrom[master]: sysfsgpio.c implement spi interface via linux sysfs
by Xiang Wang (Code Review) 09 Jan '21

09 Jan '21

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/49254 ) Change subject: sysfsgpio.c implement spi interface via linux sysfs ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I have tested it on my raspberry pi zero, it works, but the speed is very slow. -- To view, visit https://review.coreboot.org/c/flashrom/+/49254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1bc47ef8011bba560326b501a80869340bb9f733 Gerrit-Change-Number: 49254 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shawn C <citypw(a)hardenedlinux.org> Gerrit-Comment-Date: Sat, 09 Jan 2021 03:35:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: programmer.h: remove unused interfaces of bitbang_spi_master
by Xiang Wang (Code Review) 09 Jan '21

09 Jan '21

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/49256 ) Change subject: programmer.h: remove unused interfaces of bitbang_spi_master ...................................................................... programmer.h: remove unused interfaces of bitbang_spi_master Change-Id: I68e5fc39cf831e3b7d98a6e4797b36584c6082e8 Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M developerbox_spi.c M programmer.h 2 files changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/56/49256/1 diff --git a/developerbox_spi.c b/developerbox_spi.c index 4ff2fb6..bc398d5 100644 --- a/developerbox_spi.c +++ b/developerbox_spi.c @@ -114,18 +114,11 @@ return !!(cp210x_gpio_get() & (1 << DEVELOPERBOX_SPI_MISO)); } -static void cp210x_bitbang_set_sck_set_mosi(int sck, int mosi) -{ - cp210x_gpio_set(sck << DEVELOPERBOX_SPI_SCK | mosi << DEVELOPERBOX_SPI_MOSI, - 1 << DEVELOPERBOX_SPI_SCK | 1 << DEVELOPERBOX_SPI_MOSI); -} - static const struct bitbang_spi_master bitbang_spi_master_cp210x = { .set_cs = cp210x_bitbang_set_cs, .set_sck = cp210x_bitbang_set_sck, .set_mosi = cp210x_bitbang_set_mosi, .get_miso = cp210x_bitbang_get_miso, - .set_sck_set_mosi = cp210x_bitbang_set_sck_set_mosi, }; static int developerbox_spi_shutdown(void *data) diff --git a/programmer.h b/programmer.h index 5dbbaf9..e501d7f 100644 --- a/programmer.h +++ b/programmer.h @@ -191,9 +191,6 @@ int (*get_miso) (void); void (*request_bus) (void); void (*release_bus) (void); - /* optional functions to optimize xfers */ - void (*set_sck_set_mosi) (int sck, int mosi); - int (*set_sck_get_miso) (int sck); /* Length of half a clock period in usecs. */ unsigned int half_period; }; -- To view, visit https://review.coreboot.org/c/flashrom/+/49256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I68e5fc39cf831e3b7d98a6e4797b36584c6082e8 Gerrit-Change-Number: 49256 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: bitbang-spi.c: support clock polarity and phase
by Xiang Wang (Code Review) 09 Jan '21

09 Jan '21

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/49255 ) Change subject: bitbang-spi.c: support clock polarity and phase ...................................................................... bitbang-spi.c: support clock polarity and phase Change-Id: I04c1dfe132d756119229b27c3cd611d1be1abc8d Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M bitbang_spi.c 1 file changed, 71 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/55/49255/1 diff --git a/bitbang_spi.c b/bitbang_spi.c index c402119..9003d81 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -2,6 +2,7 @@ * This file is part of the flashrom project. * * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger + * Copyright (C) 2021 HardenedLinux * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,6 +22,26 @@ #include "programmer.h" #include "spi.h" +/* + * SPI has four modes + * + * These four modes are determined by two factors. + * These two factors are cpol(clock polarity) and cpha(clock phase). + * + * cpol determines the sck level, when the bus is idle. + * + * There are two sck changes in a cycle. + * If the data transmission occurs in the first sck change then cpha=0, otherwise cpha=1. + * + * Mode = 0 -> cpol = 0, cpha = 0 + * Mode = 1 -> cpol = 0, cpha = 1 + * Mode = 2 -> cpol = 1, cpha = 0 + * Mode = 3 -> cpol = 1, cpha = 1 + */ + +static int cpol; /* Clock Polarity */ +static int cpha; /* Clock Phase */ + /* Note that CS# is active low, so val=0 means the chip is active. */ static void bitbang_spi_set_cs(const struct bitbang_spi_master * const master, int val) { @@ -44,56 +65,47 @@ master->release_bus(); } -static void bitbang_spi_set_sck_set_mosi(const struct bitbang_spi_master * const master, int sck, int mosi) +static void bitbang_spi_set_mosi(const struct bitbang_spi_master * const master, int mosi) { - if (master->set_sck_set_mosi) { - master->set_sck_set_mosi(sck, mosi); - return; - } - - master->set_sck(sck); master->set_mosi(mosi); } -static int bitbang_spi_set_sck_get_miso(const struct bitbang_spi_master * const master, int sck) +static int bitbang_spi_get_miso(const struct bitbang_spi_master * const master) { - if (master->set_sck_get_miso) - return master->set_sck_get_miso(sck); - - master->set_sck(sck); return master->get_miso(); } -static uint8_t bitbang_spi_read_byte(const struct bitbang_spi_master *master) +static uint8_t bitbang_spi_xfer(const struct bitbang_spi_master * const master, uint8_t val) { uint8_t ret = 0; - int i; + for (int i = 0; i < 8; i++) { + if (cpha == 0) { + bitbang_spi_set_mosi(master, (val & 0x80)==0x80); + val = val << 1; + programmer_delay(master->half_period); + } + bitbang_spi_set_sck(master, !cpol); + if (cpha == 0) { + ret = ret << 1; + ret |= bitbang_spi_get_miso(master); + programmer_delay(master->half_period); + } - for (i = 7; i >= 0; i--) { - if (i == 0) - bitbang_spi_set_sck_set_mosi(master, 0, 0); - else - bitbang_spi_set_sck(master, 0); - programmer_delay(master->half_period); - ret <<= 1; - ret |= bitbang_spi_set_sck_get_miso(master, 1); - programmer_delay(master->half_period); + if (cpha == 1) { + bitbang_spi_set_mosi(master, (val & 0x80)==0x80); + val = val << 1; + programmer_delay(master->half_period); + } + bitbang_spi_set_sck(master, cpol); + if (cpha == 1) { + ret = ret << 1; + ret |= bitbang_spi_get_miso(master); + programmer_delay(master->half_period); + } } return ret; } -static void bitbang_spi_write_byte(const struct bitbang_spi_master *master, uint8_t val) -{ - int i; - - for (i = 7; i >= 0; i--) { - bitbang_spi_set_sck_set_mosi(master, 0, (val >> i) & 1); - programmer_delay(master->half_period); - bitbang_spi_set_sck(master, 1); - programmer_delay(master->half_period); - } -} - static int bitbang_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, @@ -107,13 +119,15 @@ * programmer to use its own SPI engine for native accesses. */ bitbang_spi_request_bus(master); + programmer_delay(master->half_period); bitbang_spi_set_cs(master, 0); - for (i = 0; i < writecnt; i++) - bitbang_spi_write_byte(master, writearr[i]); - for (i = 0; i < readcnt; i++) - readarr[i] = bitbang_spi_read_byte(master); + programmer_delay(master->half_period); - bitbang_spi_set_sck(master, 0); + for (i = 0; i < writecnt; i++) + bitbang_spi_xfer(master, writearr[i]); + for (i = 0; i < readcnt; i++) + readarr[i] = bitbang_spi_xfer(master, 0); + programmer_delay(master->half_period); bitbang_spi_set_cs(master, 1); programmer_delay(master->half_period); @@ -155,13 +169,29 @@ return ERROR_FLASHROM_BUG; } + char *mode = extract_programmer_param("mode"); + if (mode) { + if (strlen(mode)) { + char *endptr; + int v = strtol(mode, &endptr, 0); + if (mode == endptr || v > 3 || v < 0) { + msg_perr("bitbang spi only work with mode 0-3\n"); + free(mode); + return ERROR_FLASHROM_BUG; + } + cpol = (v >> 1) & 1; + cpha = (v >> 0) & 1; + } + free(mode); + } + mst.data = master; register_spi_master(&mst); /* Only mess with the bus if we're sure nobody else uses it. */ bitbang_spi_request_bus(master); bitbang_spi_set_cs(master, 1); - bitbang_spi_set_sck_set_mosi(master, 0, 0); + bitbang_spi_set_sck(master, cpol); /* FIXME: Release SPI bus here and request it again for each command or * don't release it now and only release it on programmer shutdown? */ -- To view, visit https://review.coreboot.org/c/flashrom/+/49255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I04c1dfe132d756119229b27c3cd611d1be1abc8d Gerrit-Change-Number: 49255 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: sysfsgpio.c implement spi interface via linux sysfs
by Xiang Wang (Code Review) 09 Jan '21

09 Jan '21

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/49254 ) Change subject: sysfsgpio.c implement spi interface via linux sysfs ...................................................................... sysfsgpio.c implement spi interface via linux sysfs Linux can operate gpio through sysfs, this patch implements a bitbang spi interface through sysfs. Through this patch, some SBC can be used as flash programmers. Change-Id: I1bc47ef8011bba560326b501a80869340bb9f733 Signed-off-by: Xiang Wang <merle(a)hardenedliux.org> --- M Makefile M flashrom.c M programmer.h A sysfsgpio.c 4 files changed, 280 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/49254/1 diff --git a/Makefile b/Makefile index 1f7ea46..b4383a2 100644 --- a/Makefile +++ b/Makefile @@ -482,6 +482,7 @@ ifeq ($(TARGET_OS), Linux) CONFIG_LINUX_I2C_HELPER = yes +CONFIG_SYSFSGPIO = yes endif ############################################################################### @@ -797,6 +798,8 @@ # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no +CONFIG_SYSFSGPIO ?= no + # Disable all features if CONFIG_NOTHING=yes is given unless CONFIG_EVERYTHING was also set ifeq ($(CONFIG_NOTHING), yes) ifeq ($(CONFIG_EVERYTHING), yes) @@ -1026,6 +1029,11 @@ PROGRAMMER_OBJS += realtek_mst_i2c_spi.o endif +ifeq ($(CONFIG_SYSFSGPIO), yes) +FEATURE_CFLAGS += -D'CONFIG_SYSFSGPIO=1' +PROGRAMMER_OBJS += sysfsgpio.o +endif + ifneq ($(NEED_LIBFTDI), ) FTDILIBS := $(call debug_shell,[ -n "$(PKG_CONFIG_LIBDIR)" ] && export PKG_CONFIG_LIBDIR="$(PKG_CONFIG_LIBDIR)" ; $(PKG_CONFIG) --libs libftdi1 || $(PKG_CONFIG) --libs libftdi || printf "%s" "-lftdi -lusb") FEATURE_CFLAGS += $(call debug_shell,grep -q "FT232H := yes" .features && printf "%s" "-D'HAVE_FT232H=1'") diff --git a/flashrom.c b/flashrom.c index c89abad..dc9834b 100644 --- a/flashrom.c +++ b/flashrom.c @@ -533,6 +533,18 @@ }, #endif +#if CONFIG_SYSFSGPIO == 1 + { + .name = "sysfsgpio", + .type = OTHER, + .devs.note = "bitbang spi interface using gpio via sysfs\n", + .init = sysfsgpio_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + {0}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; diff --git a/programmer.h b/programmer.h index d66d239..5dbbaf9 100644 --- a/programmer.h +++ b/programmer.h @@ -142,6 +142,9 @@ #if CONFIG_REALTEK_MST_I2C_SPI == 1 PROGRAMMER_REALTEK_MST_I2C_SPI, #endif +#if CONFIG_SYSFSGPIO == 1 + PROGRAMMER_SYSFSGPIO, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -599,6 +602,11 @@ int ni845x_spi_init(void); #endif +/* sysfsgpio.c */ +#if CONFIG_SYSFSGPIO == 1 +int sysfsgpio_init(void); +#endif + /* flashrom.c */ struct decode_sizes { uint32_t parallel; diff --git a/sysfsgpio.c b/sysfsgpio.c new file mode 100644 index 0000000..1b3dff7 --- /dev/null +++ b/sysfsgpio.c @@ -0,0 +1,252 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2021 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This driver implements a bitbang spi interface using gpio via sysfs. */ + +#include "platform.h" + +#if IS_LINUX + +#include <errno.h> +#include <fcntl.h> +#include <unistd.h> +#include <stdlib.h> +#include <string.h> +#include <limits.h> +#include <sys/stat.h> +#include <sys/types.h> +#include "programmer.h" + +#define GPIO_EXPORT "/sys/class/gpio/export" +#define GPIO_UNEXPORT "/sys/class/gpio/unexport" +#define GPIO_PATH "/sys/class/gpio/gpio%d/" +#define GPIO_VALUE "/sys/class/gpio/gpio%d/value" +#define GPIO_DIRECTION "/sys/class/gpio/gpio%d/direction" + +#define EXIST_PATH(path) (access((path), F_OK) == 0) + +struct pin_desc { + const char *name; + int pin; + int fd_direction; + int fd_value; +}; + +static struct pin_desc pin_cs = { + .name = "cs", + .fd_direction = -1, + .fd_value = -1 +}; + +static struct pin_desc pin_sck = { + .name = "sck", + .fd_direction = -1, + .fd_value = -1 +}; + +static struct pin_desc pin_mosi = { + .name = "mosi", + .fd_direction = -1, + .fd_value = -1 +}; + +static struct pin_desc pin_miso = { + .name = "miso", + .fd_direction = -1, + .fd_value = -1 +}; + +static int open_write_close(const char *path, const char *str) +{ + int fd = open(path, O_WRONLY); + if (fd < 0) { + msg_perr("Error: failed to open %s\n", path); + return -1; + } + int ret = write(fd, str, strlen(str)); + close(fd); + if (ret == (int)strlen(str)) + return 0; + msg_perr("Error: failed to write %s to %s", str, path); + return -1; +} + +static int export_sysfsgpio(struct pin_desc *desc) +{ + char s[64]; + + snprintf(s, sizeof(s), GPIO_PATH, desc->pin); + if (!EXIST_PATH(s)) { + snprintf(s, sizeof(s), "%d", desc->pin); + if (open_write_close(GPIO_EXPORT, s)) + return -1; + } + + snprintf(s, sizeof(s), GPIO_DIRECTION, desc->pin); + desc->fd_direction = open(s, O_WRONLY); + if (desc->fd_direction < 0) { + msg_perr("Error: failed to open %s\n", s); + return -1; + } + + snprintf(s, sizeof(s), GPIO_VALUE, desc->pin); + desc->fd_value = open(s, O_RDONLY); + if (desc->fd_value < 0) { + msg_perr("Error: failed to open %s\n", s); + return -1; + } + + if (write(desc->fd_direction, "in", 2) != 2) { + msg_perr("Error: failed to set %s as input", desc->name); + return -1; + } + + return 0; +} + +static void unexport_sysfsgpio(struct pin_desc *desc) +{ + char s[64]; + + if (desc->fd_direction >= 0) + close(desc->fd_direction); + if (desc->fd_value >= 0) + close(desc->fd_value); + + snprintf(s, sizeof(s), GPIO_PATH, desc->pin); + if (EXIST_PATH(s)) { + snprintf(s, sizeof(s), "%d", desc->pin); + open_write_close(GPIO_UNEXPORT, s); + } + + desc->fd_value = -1; + desc->fd_direction = -1; +} + +static void sysfsgpio_set(struct pin_desc *desc, int val) +{ + const char *s = val ? "high" : "low"; + int count = val ? 4 : 3; + if (write(desc->fd_direction, s, count) != count) + msg_perr("Error: failed to set %s\n", desc->name); +} + +static int sysfsgpio_get(struct pin_desc *desc) +{ + char v; + lseek(desc->fd_value, 0, SEEK_SET); + if (read(desc->fd_value, &v, 1) != 1) + msg_perr("Error: failed to get %s\n", desc->name); + return v != '0'; +} + +static void sysfsgpio_set_cs(int val) +{ + sysfsgpio_set(&pin_cs, val); +} + +static void sysfsgpio_set_sck(int val) +{ + sysfsgpio_set(&pin_sck, val); +} + +static void sysfsgpio_set_mosi(int val) +{ + sysfsgpio_set(&pin_mosi, val); +} + +static int sysfsgpio_get_miso(void) +{ + return sysfsgpio_get(&pin_miso); +} + +static struct bitbang_spi_master bitbang_spi_sysfsgpio = { + .set_cs = sysfsgpio_set_cs, + .set_sck = sysfsgpio_set_sck, + .set_mosi = sysfsgpio_set_mosi, + .get_miso = sysfsgpio_get_miso, +}; + +static int shutdown_sysfsgpio(void *data) +{ + unexport_sysfsgpio(&pin_cs); + unexport_sysfsgpio(&pin_sck); + unexport_sysfsgpio(&pin_mosi); + unexport_sysfsgpio(&pin_miso); + return 0; +} + +static int atoi_s(const char *s, int allstr, long *out) +{ + char *endptr; + errno = 0; + *out = strtol(s, &endptr, 0); + if ((errno == ERANGE && (*out == LONG_MAX || *out == LONG_MIN)) + || errno || s == endptr) + return -1; + if (allstr && *endptr != '\0') + return -1; + return 0; +} + +int sysfsgpio_init(void) +{ + if (register_shutdown(shutdown_sysfsgpio, NULL)) + return -1; + + /* parameter format: pins=cs_pin:sck_pin:mosi_pin:miso_pin */ + char *pins = extract_programmer_param("pins"); + int pins_inited = 0; + do { + struct pin_desc *pins_tab[] = { + &pin_cs, &pin_sck, &pin_mosi, &pin_miso + }; + if (!(pins && strlen(pins))) + break; + char *token = strtok(pins, ":"); + for (unsigned i = 0; i < ARRAY_SIZE(pins_tab); i++) { + long v; + if (!token) + break; + if (atoi_s(token, 1, &v)) + break; + pins_tab[i]->pin = v; + if (export_sysfsgpio(pins_tab[i])) + break; + token = strtok(NULL, ":"); + pins_inited = (i + 1 == ARRAY_SIZE(pins_tab)); + } + } while (0); + if (pins) + free(pins); + if (!pins_inited) + return 1; + + msg_pdbg("sysfsgpio: CS pin is %d\n", pin_cs.pin); + msg_pdbg("sysfsgpio: SCK pin is %d\n", pin_sck.pin); + msg_pdbg("sysfsgpio: MOSI pin is %d\n", pin_mosi.pin); + msg_pdbg("sysfsgpio: MISO pin is %d\n", pin_miso.pin); + msg_pdbg("sysfsgpio: half_period is %d\n", + bitbang_spi_sysfsgpio.half_period); + + if (register_spi_bitbang_master(&bitbang_spi_sysfsgpio)) { + msg_perr("sysfsgpio bitbang SPI master init failed!\n"); + return 1; + } + + return 0; +} + +#endif -- To view, visit https://review.coreboot.org/c/flashrom/+/49254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1bc47ef8011bba560326b501a80869340bb9f733 Gerrit-Change-Number: 49254 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips.c: Mark GD25LQ128C/D as TEST_OK_PREW
by Angel Pons (Code Review) 07 Jan '21

07 Jan '21

Attention is currently required from: Alan Green. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/49229 ) Change subject: flashchips.c: Mark GD25LQ128C/D as TEST_OK_PREW ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/49229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic5329ebe81b6c1eabfb594f7f7affb3fd460db6b Gerrit-Change-Number: 49229 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alan Green <avg(a)google.com> Gerrit-Comment-Date: Thu, 07 Jan 2021 22:24:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: flashchips.c: Mark GD25LQ128C/D as TEST_OK_PREW
by Alan Green (Code Review) 07 Jan '21

07 Jan '21

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/49229 ) Change subject: flashchips.c: Mark GD25LQ128C/D as TEST_OK_PREW ...................................................................... flashchips.c: Mark GD25LQ128C/D as TEST_OK_PREW I have successfully probed/read/erased/written a GD25LQ128D, so marking this entry as tested. Signed-off-by: Alan Green <avg(a)google.com> Change-Id: Ic5329ebe81b6c1eabfb594f7f7affb3fd460db6b --- M flashchips.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/29/49229/1 diff --git a/flashchips.c b/flashchips.c index 7590dff..38b0bfd 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6242,7 +6242,7 @@ .page_size = 256, /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = -- To view, visit https://review.coreboot.org/c/flashrom/+/49229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic5329ebe81b6c1eabfb594f7f7affb3fd460db6b Gerrit-Change-Number: 49229 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips: upstream AT25SF128A from chromiumos
by Alan Green (Code Review) 06 Jan '21

06 Jan '21

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/37543 ) Change subject: flashchips: upstream AT25SF128A from chromiumos ...................................................................... flashchips: upstream AT25SF128A from chromiumos Upstream the AT25SF128A chip from chromiumos repository. Change-Id: I6349aa41eee0c997aaa507383aff7ce26441d24f --- M flashchips.c M flashchips.h 2 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/43/37543/1 diff --git a/flashchips.c b/flashchips.c index 4324c11..fc4cdff 100644 --- a/flashchips.c +++ b/flashchips.c @@ -2293,6 +2293,44 @@ { .vendor = "Atmel", + .name = "AT25SF128A", + .bustype = BUS_SPI, + .manufacture_id = ATMEL_ID, + .model_id = ATMEL_AT25SF128A, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PR, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp4_srwd, + .unlock = spi_disable_blockprotect_bp4_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Atmel", .name = "AT25SF161", .bustype = BUS_SPI, .manufacture_id = ATMEL_ID, diff --git a/flashchips.h b/flashchips.h index 2c2da6c..5609527 100644 --- a/flashchips.h +++ b/flashchips.h @@ -151,6 +151,7 @@ #define ATMEL_AT25SF081 0x8501 #define ATMEL_AT25SF161 0x8601 #define ATMEL_AT25SL128A 0x4218 +#define ATMEL_AT25SF128A 0x8901 /* Adesto AT25SF128A */ #define ATMEL_AT26DF041 0x4400 #define ATMEL_AT26DF081 0x4500 /* guessed, no datasheet available */ #define ATMEL_AT26DF081A 0x4501 -- To view, visit https://review.coreboot.org/c/flashrom/+/37543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6349aa41eee0c997aaa507383aff7ce26441d24f Gerrit-Change-Number: 37543 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips.c: Take GD25LQ128C/D from downstream
by Alan Green (Code Review) 06 Jan '21

06 Jan '21

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/35478 ) Change subject: flashchips.c: Take GD25LQ128C/D from downstream ...................................................................... flashchips.c: Take GD25LQ128C/D from downstream Take the diffs for GD25LQ128C/D from the ChromiumOS flashrom repo. This chips was added in Chromium OS `commit 62cd8106` by furquan(a)google.com on 2016-07-18, and has been marked tested. Signed-off-by: Alan Green <avg(a)google.com> Change-Id: I4358392520507ddbfc654feb49fa982d49db2f28 --- M flashchips.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/35478/1 diff --git a/flashchips.c b/flashchips.c index 3994c93..5c797fd 100644 --- a/flashchips.c +++ b/flashchips.c @@ -5894,7 +5894,7 @@ .page_size = 256, /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -5916,8 +5916,7 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_bp4_srwd, - .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1695, 1950}, -- To view, visit https://review.coreboot.org/c/flashrom/+/35478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I4358392520507ddbfc654feb49fa982d49db2f28 Gerrit-Change-Number: 35478 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

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