December 2020 - flashrom-gerrit

Change in flashrom[master]: sb600spi.c: add rev 0x51 to the leading comment block
by Idwer Vollering (Code Review) 07 Feb '21

07 Feb '21

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48879 ) Change subject: sb600spi.c: add rev 0x51 to the leading comment block ...................................................................... sb600spi.c: add rev 0x51 to the leading comment block Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Change-Id: Ic74cff04f2d1fd92ad92aa37f71e5852f02d86a6 --- M sb600spi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/48879/1 diff --git a/sb600spi.c b/sb600spi.c index ef9da4b..b9560e2 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -127,7 +127,7 @@ * found on both Stoney Ridge and Zen platforms. * * The revisions I have found by searching various lspci - * outputs are as follows: 0x4b, 0x59 & 0x61. + * outputs are as follows: 0x4b, 0x51, 0x59 & 0x61. */ } else if (rev == 0x4b || rev == 0x51 || rev == 0x59 || rev == 0x61) { msg_pdbg("Promontory (rev 0x%02x) detected.\n", rev); -- To view, visit https://review.coreboot.org/c/flashrom/+/48879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic74cff04f2d1fd92ad92aa37f71e5852f02d86a6 Gerrit-Change-Number: 48879 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in flashrom[master]: Fix building with musl libc
by Evgeny Zinoviev (Code Review) 07 Feb '21

07 Feb '21

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48314 ) Change subject: Fix building with musl libc ...................................................................... Fix building with musl libc AFAIK, this shouldn't break anything, as glibc just includes fcntl.h from sys/fcntl.h. Change-Id: Ie74ae584619ae8cbc188855aedcf5596d7afcfc8 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M i2c_helper_linux.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/14/48314/1 diff --git a/i2c_helper_linux.c b/i2c_helper_linux.c index 0703518..5c191f9 100644 --- a/i2c_helper_linux.c +++ b/i2c_helper_linux.c @@ -17,7 +17,7 @@ #include <errno.h> #include <stdio.h> #include <string.h> -#include <sys/fcntl.h> +#include <fcntl.h> #include <sys/ioctl.h> #include <unistd.h> -- To view, visit https://review.coreboot.org/c/flashrom/+/48314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie74ae584619ae8cbc188855aedcf5596d7afcfc8 Gerrit-Change-Number: 48314 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

3 3

Change in flashrom[master]: cbtable.c: don't assume high addresses can fully map 1 MiB
by Edward O'Callaghan (Code Review) 25 Jan '21

25 Jan '21

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/37240 ) Change subject: cbtable.c: don't assume high addresses can fully map 1 MiB ...................................................................... cbtable.c: don't assume high addresses can fully map 1 MiB Forward port the downstream `commit b17e9e41838`. When using a forwarding table entry for finding the coreboot table don't assume one has access to a full 1 MiB where the forwarding table entry points to. The reason is that the 1 MiB may cover address regions that have differing cacheability type. As such the kernel will complain and the mapping will fail. Instead, check the header first then map in the bytes that it indicates after sanity validation. That way there is no attempt at requesting an invalid mapping that spans different memory cacheability attributes. BUG=b:66681446 BRANCH=None TEST=Can successfully run 'flashrom -p host --wp-status' on kahlee without generating PAT errors. Original-Change-Id: Ic6c5832b069300cced66e11f4ca4a0bbc6e496de Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/685608 Original-Reviewed-by: Martin Roth <martinroth(a)chromium.org> Original-Reviewed-by: Justin TerAvest <teravest(a)chromium.org> Change-Id: I43705c19dd7c816098d03f528bde6f180c4c8f24 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M cbtable.c 1 file changed, 61 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/40/37240/1 diff --git a/cbtable.c b/cbtable.c index e566840..38a9f11 100644 --- a/cbtable.c +++ b/cbtable.c @@ -210,6 +210,66 @@ return NULL; } +static struct lb_header *find_lb_table_remap(unsigned long start_addr, + uint8_t **table_area) +{ + size_t offset; + unsigned long addr, end; + size_t mapping_size; + void *base; + + mapping_size = getpagesize(); + offset = start_addr % getpagesize(); + start_addr -= offset; + + base = physmap_ro("high tables", start_addr, mapping_size); + if (ERROR_PTR == base) { + msg_perr("Failed getting access to coreboot high tables.\n"); + return NULL; + } + + for (addr = offset, end = getpagesize(); addr < end; addr += 16) { + struct lb_record *recs; + struct lb_header *head; + + /* No more headers to check. */ + if (end - addr < sizeof(*head)) + return NULL; + + head = (struct lb_header *)(((char *)base) + addr); + + if (!lb_header_valid(head, addr)) + continue; + + if (mapping_size - addr < head->table_bytes + sizeof(*head)) { + size_t prev_mapping_size = mapping_size; + mapping_size = head->table_bytes + sizeof(*head); + mapping_size += addr; + mapping_size += getpagesize() - + (mapping_size % getpagesize()); + physunmap(base, prev_mapping_size); + base = physmap_ro("high tables", start_addr, + mapping_size); + if (ERROR_PTR == base) { + msg_perr("Failed getting access to coreboot high tables.\n"); + return NULL; + } + } + + head = (struct lb_header *)(((char *)base) + addr); + recs = + (struct lb_record *)(((char *)base) + addr + sizeof(*head)); + if (!lb_table_valid(head, recs)) + continue; + msg_pdbg("Found coreboot table at 0x%08lx.\n", addr); + *table_area = base; + return head; + } + + physunmap(base, mapping_size); + return NULL; +} + static void find_mainboard(struct lb_record *ptr, unsigned long addr) { struct lb_mainboard *rec; @@ -283,15 +343,8 @@ (((char *)lb_table) + lb_table->header_bytes); if (forward->tag == LB_TAG_FORWARD) { start = forward->forward; - start &= ~(getpagesize() - 1); physunmap_unaligned(table_area, BYTES_TO_MAP); - // FIXME: table_area is never unmapped below, nor is it unmapped above in the no-forward case - table_area = physmap_ro_unaligned("high tables", start, BYTES_TO_MAP); - if (ERROR_PTR == table_area) { - msg_perr("Failed getting access to coreboot high tables.\n"); - return -1; - } - lb_table = find_lb_table(table_area, 0x00000, 0x1000); + lb_table = find_lb_table_remap(start, &table_area); } } -- To view, visit https://review.coreboot.org/c/flashrom/+/37240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I43705c19dd7c816098d03f528bde6f180c4c8f24 Gerrit-Change-Number: 37240 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

5 13

Change in flashrom[master]: Simplifying the initialisation flow for it85spi
by Anastasia Klimchuk (Code Review) 20 Jan '21

20 Jan '21

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48196 ) Change subject: Simplifying the initialisation flow for it85spi ...................................................................... Simplifying the initialisation flow for it85spi 1) Inlining it85xx_spi_common_init since it's only used once in it85xx_spi_init, after inlining ret value is not needed. 2) Creating it86_init_error section to ensure that data is freed if error happened in initialisaton flow. BUG=b:172876667 TEST=builds Change-Id: Iac1b4ae9c6f34c5265e729ae0a80024800c3c272 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M it85spi.c 1 file changed, 32 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/48196/1 diff --git a/it85spi.c b/it85spi.c index 6215515..52b09b1 100644 --- a/it85spi.c +++ b/it85spi.c @@ -289,11 +289,18 @@ .write_aai = default_spi_write_aai, }; -static int it85xx_spi_common_init(struct superio s) +int it85xx_spi_init(struct superio s) { chipaddr base; + struct it85spi_data *data; + msg_pdbg("%s():%d superio.vendor=0x%02x\n", __func__, __LINE__, s.vendor); - struct it85spi_data *data = calloc(1, sizeof(struct it85spi_data)); + if (!(internal_buses_supported & BUS_FWH)) { + msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__); + return 1; + } + + data = calloc(1, sizeof(struct it85spi_data)); if (!data) { msg_perr("Unable to allocate space for extra SPI master data.\n"); return SPI_GENERIC_ERROR; @@ -301,12 +308,8 @@ spi_master_it85xx.data = data; - msg_pdbg("%s():%d superio.vendor=0x%02x\n", __func__, __LINE__, - s.vendor); - if (register_shutdown(it85xx_shutdown, data)) { - free(data); - return 1; + goto it85spi_init_error; } #ifdef LPC_IO @@ -334,9 +337,9 @@ * Major TODO here, and it will be a lot of work. */ base = (chipaddr)physmap("it85 communication", 0xFFFFF000, 0x1000); - if (base == (chipaddr)ERROR_PTR) - free(data); - return 1; + if (base == (chipaddr)ERROR_PTR) { + goto it85spi_init_error; + } msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__, (unsigned int)base); @@ -344,37 +347,27 @@ data->ce_low = (unsigned char *)(base + 0xD00); /* 0xFFFFFD00 */ #endif + msg_pdbg("%s: internal_buses_supported=0x%x\n", __func__, + internal_buses_supported); + /* Check for FWH because IT85 listens to FWH cycles. + * FIXME: The big question is whether FWH cycles are necessary + * for communication even if LPC_IO is defined. + */ + if (internal_buses_supported & BUS_FWH) + msg_pdbg("Registering IT85 SPI.\n"); + /* FIXME: Really leave FWH enabled? We can't use this region + * anymore since accessing it would mess up IT85 communication. + * If we decide to disable FWH for this region, we should print + * a debug message about it. + */ + /* Set this as SPI controller. */ + register_spi_master(&spi_master_it85xx); + return 0; -} -int it85xx_spi_init(struct superio s) -{ - int ret; - - if (!(internal_buses_supported & BUS_FWH)) { - msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__); - return 1; - } - ret = it85xx_spi_common_init(s); - msg_pdbg("FWH: %s():%d ret=%d\n", __func__, __LINE__, ret); - if (!ret) { - msg_pdbg("%s: internal_buses_supported=0x%x\n", __func__, - internal_buses_supported); - /* Check for FWH because IT85 listens to FWH cycles. - * FIXME: The big question is whether FWH cycles are necessary - * for communication even if LPC_IO is defined. - */ - if (internal_buses_supported & BUS_FWH) - msg_pdbg("Registering IT85 SPI.\n"); - /* FIXME: Really leave FWH enabled? We can't use this region - * anymore since accessing it would mess up IT85 communication. - * If we decide to disable FWH for this region, we should print - * a debug message about it. - */ - /* Set this as SPI controller. */ - register_spi_master(&spi_master_it85xx); - } - return ret; +it85spi_init_error: + free(data); + return 1; } #endif -- To view, visit https://review.coreboot.org/c/flashrom/+/48196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iac1b4ae9c6f34c5265e729ae0a80024800c3c272 Gerrit-Change-Number: 48196 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

3 22

Change in flashrom[master]: it85spi.c: Factor out global state
by Anastasia Klm (Code Review) 18 Jan '21

18 Jan '21

Anastasia Klm has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47655 ) Change subject: it85spi.c: Factor out global state ...................................................................... it85spi.c: Factor out global state Moves global state into spi_master data. BUGS=b:172876667 Change-Id: I389d34d62e753c012910aa5ff24a496b24a4753c Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M it85spi.c 1 file changed, 71 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/55/47655/1 diff --git a/it85spi.c b/it85spi.c index b998790..d6f39a4 100644 --- a/it85spi.c +++ b/it85spi.c @@ -73,11 +73,26 @@ #define INDIRECT_WRITE(base, value) OUTB(value, (base) + 4) #endif /* LPC_IO */ -#ifdef LPC_IO -static unsigned int shm_io_base; -#endif -static unsigned char *ce_high, *ce_low; -static int it85xx_scratch_rom_reenter = 0; +struct it85_data { + unsigned int shm_io_base; + unsigned char *ce_high, *ce_low; + int it85xx_scratch_rom_reenter; +}; + +static int it85xx_spi_send_command(const struct flashctx *flash, + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr); + +static struct spi_master spi_master_it85xx = { + .max_data_read = 64, + .max_data_write = 64, + .command = it85xx_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, +}; /* This function will poll the keyboard status register until either * an expected value shows up, or the timeout is reached. @@ -106,12 +121,12 @@ /* IT8502 employs a scratch RAM when flash is being updated. Call the following * two functions before/after flash erase/program. */ -static void it85xx_enter_scratch_rom(void) +static void it85xx_enter_scratch_rom(struct it85_data *data) { int ret, tries; msg_pdbg("%s():%d was called ...\n", __func__, __LINE__); - if (it85xx_scratch_rom_reenter > 0) + if (data->it85xx_scratch_rom_reenter > 0) return; #if 0 @@ -156,14 +171,14 @@ if (tries < MAX_TRY) { /* EC already runs on SRAM */ - it85xx_scratch_rom_reenter++; + data->it85xx_scratch_rom_reenter++; msg_pdbg("%s():%d * SUCCESS.\n", __func__, __LINE__); } else { msg_perr("%s():%d * Max try reached.\n", __func__, __LINE__); } } -static void it85xx_exit_scratch_rom(void) +static void it85xx_exit_scratch_rom(struct it85_data *data) { #if 0 int ret; @@ -171,7 +186,7 @@ int tries; msg_pdbg("%s():%d was called ...\n", __func__, __LINE__); - if (it85xx_scratch_rom_reenter <= 0) + if (data->it85xx_scratch_rom_reenter <= 0) return; for (tries = 0; tries < MAX_TRY; ++tries) { @@ -199,7 +214,7 @@ } if (tries < MAX_TRY) { - it85xx_scratch_rom_reenter = 0; + data->it85xx_scratch_rom_reenter = 0; msg_pdbg("%s():%d * SUCCESS.\n", __func__, __LINE__); } else { msg_perr("%s():%d * Max try reached.\n", __func__, __LINE__); @@ -217,8 +232,10 @@ static int it85xx_shutdown(void *data) { + struct it85_data *drv_data = (struct it85_data *)data; + msg_pdbg("%s():%d\n", __func__, __LINE__); - it85xx_exit_scratch_rom(); + it85xx_exit_scratch_rom(drv_data); return 0; /* FIXME: Should probably return something meaningful */ } @@ -227,31 +244,41 @@ { chipaddr base; + struct it85_data *data = calloc(1, sizeof(struct it85_data)); + if (!data) { + msg_perr("Out of memory!\n"); + return 1; + } + data->it85xx_scratch_rom_reenter = 0; + spi_master_it85xx.data = data; + msg_pdbg("%s():%d superio.vendor=0x%02x\n", __func__, __LINE__, s.vendor); - if (register_shutdown(it85xx_shutdown, NULL)) + if (register_shutdown(it85xx_shutdown, data)) { + free(data); return 1; + } #ifdef LPC_IO /* Get LPCPNP of SHM. That's big-endian. */ sio_write(s.port, LDNSEL, 0x0F); /* Set LDN to SHM (0x0F) */ - shm_io_base = (sio_read(s.port, SHM_IO_BAR0) << 8) + + data->shm_io_base = (sio_read(s.port, SHM_IO_BAR0) << 8) + sio_read(s.port, SHM_IO_BAR1); - msg_pdbg("%s():%d shm_io_base=0x%04x\n", __func__, __LINE__, - shm_io_base); + msg_pdbg("%s():%d it85_data->shm_io_base=0x%04x\n", __func__, __LINE__, + data->shm_io_base); /* These pointers are not used directly. They will be send to EC's * register for indirect access. */ base = 0xFFFFF000; - ce_high = ((unsigned char *)base) + 0xE00; /* 0xFFFFFE00 */ - ce_low = ((unsigned char *)base) + 0xD00; /* 0xFFFFFD00 */ + data->ce_high = ((unsigned char *)base) + 0xE00; /* 0xFFFFFE00 */ + data->ce_low = ((unsigned char *)base) + 0xD00; /* 0xFFFFFD00 */ /* pre-set indirect-access registers since in most of cases they are * 0xFFFFxx00. */ - INDIRECT_A0(shm_io_base, base & 0xFF); - INDIRECT_A2(shm_io_base, (base >> 16) & 0xFF); - INDIRECT_A3(shm_io_base, (base >> 24)); + INDIRECT_A0(data->shm_io_base, base & 0xFF); + INDIRECT_A2(data->shm_io_base, (base >> 16) & 0xFF); + INDIRECT_A3(data->shm_io_base, (base >> 24)); #endif #ifdef LPC_MEMORY /* FIXME: We should block accessing that region for anything else. @@ -263,28 +290,13 @@ msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__, (unsigned int)base); - ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */ - ce_low = (unsigned char *)(base + 0xD00); /* 0xFFFFFD00 */ + data->ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */ + data->ce_low = (unsigned char *)(base + 0xD00); /* 0xFFFFFD00 */ #endif return 0; } -static int it85xx_spi_send_command(const struct flashctx *flash, - unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, - unsigned char *readarr); - -static const struct spi_master spi_master_it85xx = { - .max_data_read = 64, - .max_data_write = 64, - .command = it85xx_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, -}; - int it85xx_spi_init(struct superio s) { int ret; @@ -328,42 +340,51 @@ unsigned char *readarr) { unsigned int i; + if (!(flash->mst)) { + msg_perr("No data in flash context!\n"); + return 1; + } + struct it85_data *data = (struct it85_data *) flash->mst->spi.data; + if (!data) { + msg_perr("No data in flash context!\n"); + return 1; + } - it85xx_enter_scratch_rom(); + it85xx_enter_scratch_rom(data); /* Exit scratch ROM ONLY when programmer shuts down. Otherwise, the * temporary flash state may halt the EC. */ #ifdef LPC_IO - INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); - INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/ - INDIRECT_A1(shm_io_base, (((unsigned long int)ce_low) >> 8) & 0xff); + INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_high) >> 8) & 0xff); + INDIRECT_WRITE(data->shm_io_base, 0xFF); /* Write anything to this address.*/ + INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_low) >> 8) & 0xff); #endif #ifdef LPC_MEMORY - mmio_writeb(0, ce_high); + mmio_writeb(0, data->ce_high); #endif for (i = 0; i < writecnt; ++i) { #ifdef LPC_IO - INDIRECT_WRITE(shm_io_base, writearr[i]); + INDIRECT_WRITE(data->shm_io_base, writearr[i]); #endif #ifdef LPC_MEMORY - mmio_writeb(writearr[i], ce_low); + mmio_writeb(writearr[i], data->ce_low); #endif } for (i = 0; i < readcnt; ++i) { #ifdef LPC_IO - readarr[i] = INDIRECT_READ(shm_io_base); + readarr[i] = INDIRECT_READ(data->shm_io_base); #endif #ifdef LPC_MEMORY - readarr[i] = mmio_readb(ce_low); + readarr[i] = mmio_readb(data->ce_low); #endif } #ifdef LPC_IO - INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); - INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/ + INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_high) >> 8) & 0xff); + INDIRECT_WRITE(data->shm_io_base, 0xFF); /* Write anything to this address.*/ #endif #ifdef LPC_MEMORY - mmio_writeb(0, ce_high); + mmio_writeb(0, data->ce_high); #endif return 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/47655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I389d34d62e753c012910aa5ff24a496b24a4753c Gerrit-Change-Number: 47655 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klm <aklm(a)chromium.org> Gerrit-MessageType: newchange

6 55

Change in flashrom[master]: tests/: Add programmer enumerate correspondence test
by Edward O'Callaghan (Code Review) 17 Jan '21

17 Jan '21

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47356 ) Change subject: tests/: Add programmer enumerate correspondence test ...................................................................... tests/: Add programmer enumerate correspondence test The enumerate defines within programmer.h must be aligned with the programmer dispatch table within flashrom.c. The following unit-tests tries to improve coverage here to avoid issues like we saw when ENE and MEC1308 were upstreamed. BUG=none BRANCH=none TEST=meson test Change-Id: I13efc4561f743edf51326d4b408be8715b630377 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M tests/flashrom.c M tests/tests.c M tests/tests.h 3 files changed, 94 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/56/47356/1 diff --git a/tests/flashrom.c b/tests/flashrom.c index 50464dd..9180922 100644 --- a/tests/flashrom.c +++ b/tests/flashrom.c @@ -15,6 +15,47 @@ #include <include/test.h> +/* must be before programmer.h include */ +#define CONFIG_INTERNAL 1 +#define CONFIG_DUMMY 1 +#define CONFIG_MEC1308 1 +#define CONFIG_NIC3COM 1 +#define CONFIG_NICREALTEK 1 +#define CONFIG_NICNATSEMI 1 +#define CONFIG_GFXNVIDIA 1 +#define CONFIG_RAIDEN 1 +#define CONFIG_DRKAISER 1 +#define CONFIG_SATASII 1 +#define CONFIG_ATAHPT 1 +#define CONFIG_ATAVIA 1 +#define CONFIG_ATAPROMISE 1 +#define CONFIG_IT8212 1 +#define CONFIG_FT2232_SPI 1 +#define CONFIG_SERPROG 1 +#define CONFIG_BUSPIRATE_SPI 1 +#define CONFIG_DEDIPROG 1 +#define CONFIG_DEVELOPERBOX_SPI 1 +#define CONFIG_ENE_LPC 1 +#define CONFIG_RAYER_SPI 1 +#define CONFIG_PONY_SPI 1 +#define CONFIG_NICINTEL 1 +#define CONFIG_NICINTEL_SPI 1 +#define CONFIG_NICINTEL_EEPROM 1 +#define CONFIG_OGP_SPI 1 +#define CONFIG_SATAMV 1 +#define CONFIG_LINUX_MTD 1 +#define CONFIG_LINUX_SPI 1 +#define CONFIG_LSPCON_I2C_SPI 1 +#define CONFIG_REALTEK_MST_I2C_SPI 1 +#define CONFIG_USBBLASTER_SPI 1 +#define CONFIG_MSTARDDC_SPI 1 +#define CONFIG_PICKIT2_SPI 1 +#define CONFIG_CH341A_SPI 1 +#define CONFIG_DIGILENT_SPI 1 +#define CONFIG_JLINK_SPI 1 +#define CONFIG_NI845X_SPI 1 +#define CONFIG_STLINKV3_SPI 1 + #include "programmer.h" void flashbuses_to_text_test_success(void **state) @@ -49,3 +90,54 @@ bustype = BUS_NONE; assert_string_equal(flashbuses_to_text(bustype), "None"); } + +void validate_prog_enumerates_test_success(void **state) +{ + (void) state; /* unused */ + + enum programmer prog = PROGRAMMER_INTERNAL; + const char *prog_names[] = { + "internal", + "dummy", + "mec1308", + "nic3com", + "nicrealtek", + "nicnatsemi", + "gfxnvidia", + "raiden_debug", + "drkaiser", + "satasii", + "atahpt", + "atavia", + "atapromise", + "it8212", + "ft2232_spi", + "serprog", + "buspirate_spi", + "dediprog", + "developerbox", + "ene_lpc", + "rayer_spi", + "pony_spi", + "nicintel", + "nicintel_spi", + "nicintel_eeprom", + "ogp_spi", + "satamv", + "linux_mtd", + "linux_spi", + "lspcon_i2c_spi", + "realtek_mst_i2c_spi", + "usbblaster_spi", + "mstarddc_spi", + "pickit2_spi", + "ch341a_spi", + "digilent_spi", + "jlink_spi", + "ni845x_spi", + "stlinkv3_spi", + }; + for (; prog < PROGRAMMER_INVALID; prog++) { + assert_string_equal(programmer_table[prog].name, prog_names[prog]); + } +} diff --git a/tests/tests.c b/tests/tests.c index 3124607..d2a22a5 100644 --- a/tests/tests.c +++ b/tests/tests.c @@ -46,6 +46,7 @@ const struct CMUnitTest flashrom_tests[] = { cmocka_unit_test(flashbuses_to_text_test_success), + cmocka_unit_test(validate_prog_enumerates_test_success), }; ret |= cmocka_run_group_tests_name("flashrom.c tests", flashrom_tests, NULL, NULL); diff --git a/tests/tests.h b/tests/tests.h index cb905fd..89fc7fa 100644 --- a/tests/tests.h +++ b/tests/tests.h @@ -27,6 +27,7 @@ /* flashrom.c */ void flashbuses_to_text_test_success(void **state); +void validate_prog_enumerates_test_success(void **state); /* spi25.c */ void spi_write_enable_test_success(void **state); -- To view, visit https://review.coreboot.org/c/flashrom/+/47356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I13efc4561f743edf51326d4b408be8715b630377 Gerrit-Change-Number: 47356 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: WIP: spi25_statusreg.c: restore SR contents at flashrom exit
by Nikolai Artemiev (Code Review) 12 Jan '21

12 Jan '21

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48778 ) Change subject: WIP: spi25_statusreg.c: restore SR contents at flashrom exit ...................................................................... WIP: spi25_statusreg.c: restore SR contents at flashrom exit spi_disable_blockprotect_generic() now uses register_chip_restore() to reset the chip's status register at flashrom exit. Imported from cros flashrom at `b170dd4e1d5c33b169c5` Change-Id: If2f0e73518d40519b7569f627c90a34c364df47c Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M spi25_statusreg.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/48778/1 diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 34f9ad4..5dda912 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -108,6 +108,12 @@ return readarr[0]; } +static int spi_restore_status(struct flashctx *flash, uint8_t status) +{ + msg_cdbg("restoring chip status (0x%02x)\n", status); + return spi_write_status_register(flash, status); +} + /* A generic block protection disable. * Tests if a protection is enabled with the block protection mask (bp_mask) and returns success otherwise. * Tests if the register bits are locked with the lock_mask (lock_mask). @@ -139,6 +145,9 @@ return 0; } + /* restore status register content upon exit */ + register_chip_restore(spi_restore_status, flash, status); + msg_cdbg("Some block protection in effect, disabling... "); if ((status & lock_mask) != 0) { msg_cdbg("\n\tNeed to disable the register lock first... "); -- To view, visit https://review.coreboot.org/c/flashrom/+/48778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If2f0e73518d40519b7569f627c90a34c364df47c Gerrit-Change-Number: 48778 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: Makefile: Add a DISABLE_CLOCK_GETTIME option
by Martin Lucina (Code Review) 11 Jan '21

11 Jan '21

Martin Lucina has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48796 ) Change subject: Makefile: Add a DISABLE_CLOCK_GETTIME option ...................................................................... Makefile: Add a DISABLE_CLOCK_GETTIME option Allows to force-disable the use of clock_gettime() at build time, falling back to busy-looping for udelay. This is useful when building for systems which are known to lie about the resolution of clock_gettime(). Change-Id: I645a5d3f29ffdbd24a58127ab73d7d8755304f45 Signed-off-by: Martin Lucina <martin(a)lucina.net> --- M Makefile 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/48796/1 diff --git a/Makefile b/Makefile index 1f7ea46..09b2154 100644 --- a/Makefile +++ b/Makefile @@ -1663,12 +1663,17 @@ ( echo "found."; echo "UTSNAME := yes" >> .features.tmp ) || \ ( echo "not found."; echo "UTSNAME := no" >> .features.tmp ) } 2>>$(BUILD_DETAILS_FILE) | tee -a $(BUILD_DETAILS_FILE) @printf "Checking for clock_gettime support... " | tee -a $(BUILD_DETAILS_FILE) +ifeq ($(DISABLE_CLOCK_GETTIME), yes) + @ { ( echo "disabled."; echo "CLOCK_GETTIME := no" >>.features.tmp ) } \ + 2>>$(BUILD_DETAILS_FILE) | tee -a $(BUILD_DETAILS_FILE) +else @echo "$$CLOCK_GETTIME_TEST" >.featuretest.c @printf "\nexec: %s\n" "$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -lrt .featuretest.c -o .featuretest$(EXEC_SUFFIX)" >>$(BUILD_DETAILS_FILE) @ { $(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -lrt .featuretest.c -o .featuretest$(EXEC_SUFFIX) >&2 && \ ( echo "found."; echo "CLOCK_GETTIME := yes" >>.features.tmp ) || \ ( echo "not found."; echo "CLOCK_GETTIME := no" >>.features.tmp ) } \ 2>>$(BUILD_DETAILS_FILE) | tee -a $(BUILD_DETAILS_FILE) +endif @$(DIFF) -q .features.tmp .features >/dev/null 2>&1 && rm .features.tmp || mv .features.tmp .features @rm -f .featuretest.c .featuretest$(EXEC_SUFFIX) -- To view, visit https://review.coreboot.org/c/flashrom/+/48796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I645a5d3f29ffdbd24a58127ab73d7d8755304f45 Gerrit-Change-Number: 48796 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Lucina <martin(a)lucina.net> Gerrit-MessageType: newchange

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Change in flashrom[master]: realtek_mst_i2c_spi.c: Make consistent with std=c99
by Edward O'Callaghan (Code Review) 10 Jan '21

10 Jan '21

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47909 ) Change subject: realtek_mst_i2c_spi.c: Make consistent with std=c99 ...................................................................... realtek_mst_i2c_spi.c: Make consistent with std=c99 Use 'modern' C to scope iterator declarations only to the loop constructs they are used in. BUG=none TEST=builds Change-Id: I9d9d1bf01209a7840f7b3fa2c6f7592375a74330 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M realtek_mst_i2c_spi.c 1 file changed, 4 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/09/47909/1 diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 538b07a..151f7f6 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -205,7 +205,6 @@ const unsigned char *writearr, unsigned char *readarr) { - unsigned i; int max_timeout_mul = 1; int ret = 0; @@ -262,7 +261,7 @@ ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, ctrl_reg_val); ret |= realtek_mst_i2c_spi_write_register(fd, 0x61, writearr[0]); /* opcode */ - for (i = 0; i < writecnt; ++i) + for (unsigned i = 0; i < writecnt; ++i) ret |= realtek_mst_i2c_spi_write_register(fd, 0x64 + i, writearr[i + 1]); ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, ctrl_reg_val | 0x1); if (ret) @@ -272,7 +271,7 @@ if (ret) return ret; - for (i = 0; i < readcnt; ++i) + for (unsigned i = 0; i < readcnt; ++i) ret |= realtek_mst_i2c_spi_read_register(fd, 0x67 + i, &readarr[i]); return ret; @@ -306,7 +305,6 @@ static int realtek_mst_i2c_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) { - unsigned i; int ret = 0; if (start & 0xff) @@ -339,7 +337,7 @@ uint8_t dummy; realtek_mst_i2c_spi_read_register(fd, MCU_DATA_PORT, &dummy); - for (i = 0; i < len; i += PAGE_SIZE) { + for (unsigned i = 0; i < len; i += PAGE_SIZE) { ret |= realtek_mst_i2c_spi_read_data(fd, REGISTER_ADDRESS, buf + i, min(len - i, PAGE_SIZE)); if (ret) @@ -352,7 +350,6 @@ static int realtek_mst_i2c_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len) { - unsigned i; int ret = 0; if (start & 0xff) @@ -369,7 +366,7 @@ ret |= realtek_mst_i2c_spi_write_register(fd, 0x6D, 0x02); /* write opcode */ ret |= realtek_mst_i2c_spi_write_register(fd, 0x71, (PAGE_SIZE - 1)); /* fit len=256 */ - for (i = 0; i < len; i += PAGE_SIZE) { + for (unsigned i = 0; i < len; i += PAGE_SIZE) { uint16_t page_len = min(len - i, PAGE_SIZE); if (len - i < PAGE_SIZE) ret |= realtek_mst_i2c_spi_write_register(fd, 0x71, page_len-1); -- To view, visit https://review.coreboot.org/c/flashrom/+/47909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9d9d1bf01209a7840f7b3fa2c6f7592375a74330 Gerrit-Change-Number: 47909 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: lspcon_i2c_spi.c: Make consistent with std=c99
by Edward O'Callaghan (Code Review) 10 Jan '21

10 Jan '21

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47910 ) Change subject: lspcon_i2c_spi.c: Make consistent with std=c99 ...................................................................... lspcon_i2c_spi.c: Make consistent with std=c99 Use 'modern' C to scope iterator declarations only to the loop constructs they are used in. BUG=none TEST=builds Change-Id: Id61f8416416d2f625d424760e00f94dc730105f4 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M lspcon_i2c_spi.c 1 file changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/10/47910/1 diff --git a/lspcon_i2c_spi.c b/lspcon_i2c_spi.c index 7b9f1c0..6ee2840 100644 --- a/lspcon_i2c_spi.c +++ b/lspcon_i2c_spi.c @@ -127,14 +127,13 @@ static int lspcon_i2c_spi_register_control(int fd, packet_t *packet) { - int i; int ret = lspcon_i2c_spi_write_register(fd, SWSPI_WDATA, packet->command); if (ret) return ret; /* Higher 4 bits are read size. */ int write_size = packet->data_size & 0x0f; - for (i = 0; i < write_size; ++i) { + for (unsigned i = 0; i < write_size; ++i) { ret |= lspcon_i2c_spi_write_register(fd, SWSPI_WDATA, packet->data[i]); } @@ -256,7 +255,6 @@ const unsigned char *writearr, unsigned char *readarr) { - unsigned int i; if (writecnt > 16 || readcnt > 16 || writecnt == 0) { msg_perr("%s: Invalid read/write count for send command.\n", __func__); @@ -285,7 +283,7 @@ if (ret) return ret; - for (i = 0; i < readcnt; ++i) { + for (unsigned i = 0; i < readcnt; ++i) { ret |= lspcon_i2c_spi_read_register(fd, SWSPI_RDATA, &readarr[i]); } @@ -340,7 +338,6 @@ static int lspcon_i2c_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) { - unsigned int i; int ret = 0; if (start & 0xff) return default_spi_read(flash, buf, start, len); @@ -349,7 +346,7 @@ if (fd < 0) return SPI_GENERIC_ERROR; - for (i = 0; i < len; i += PAGE_SIZE) { + for (unsigned i = 0; i < len; i += PAGE_SIZE) { ret |= lspcon_i2c_spi_map_page(fd, start + i); ret |= lspcon_i2c_spi_read_data(fd, PAGE_ADDRESS, buf + i, min(len - i, PAGE_SIZE)); } -- To view, visit https://review.coreboot.org/c/flashrom/+/47910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id61f8416416d2f625d424760e00f94dc730105f4 Gerrit-Change-Number: 47910 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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