December 2020 - flashrom-gerrit

Change in flashrom[master]: flashchips.c: Add support for XMC new spi flash types
by Edward O'Callaghan (Code Review) 30 Dec '20

30 Dec '20

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/48949 ) Change subject: flashchips.c: Add support for XMC new spi flash types ...................................................................... Patch Set 3: (3 comments) https://review.coreboot.org/c/flashrom/+/48949/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/flashrom/+/48949/3//COMMIT_MSG@16 PS3, Line 16: TEST=test Was a test actually performed? e.g., `TEST=flash image, then read it back then erased successfully.` Also no need to indent the commit message. For an example of a commit message format see https://review.coreboot.org/c/flashrom/+/44073 https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.h File flashchips.h: https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.h@814 PS1, Line 814: > two tabs needed to line up with the rest from the looks of it. Click "Resolve" on comments that were fixed. https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.c File flashchips.c: https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.c@19004 PS1, Line 19004: TEST_OK_PREW > Were these all tested? if not then you want `TEST_UNTESTED`. […] I feel like the `TEST=` line should indicate these were not actually tested from the sounds of things. So in the commit message `TEST=builds` and for each chip `.tested = TEST_UNTESTED`. -- To view, visit https://review.coreboot.org/c/flashrom/+/48949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969 Gerrit-Change-Number: 48949 Gerrit-PatchSet: 3 Gerrit-Owner: luke <sixuerain(a)qq.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Carl-Daniel Hailfinger <hailfinger(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Uwe Hermann <uwe(a)hermann-uwe.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 30 Dec 2020 11:28:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: flashchips.c: Add support for XMC new spi flash types
by luke (Code Review) 29 Dec '20

29 Dec '20

Hello build bot (Jenkins), Edward O'Callaghan, Angel Pons, Nikolai Artemiev, Carl-Daniel Hailfinger, Uwe Hermann, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/48949 to look at the new patch set (#3). Change subject: flashchips.c: Add support for XMC new spi flash types ...................................................................... flashchips.c: Add support for XMC new spi flash types XM25QU64C XM25QU128C XM25QU256C XM25QH64C XM25QH128C XM25QH256C TEST=test Signed-off-by: Luke He <sixuerain(a)qq.com> Change-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969 --- M flashchips.c M flashchips.h 2 files changed, 245 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/49/48949/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/48949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969 Gerrit-Change-Number: 48949 Gerrit-PatchSet: 3 Gerrit-Owner: luke <sixuerain(a)qq.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Carl-Daniel Hailfinger <hailfinger(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Uwe Hermann <uwe(a)hermann-uwe.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: flashchips.c: Add support for XMC new spi flash types
by luke (Code Review) 29 Dec '20

29 Dec '20

luke has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/49010 ) Change subject: flashchips.c: Add support for XMC new spi flash types ...................................................................... flashchips.c: Add support for XMC new spi flash types XM25QU64C XM25QU128C XM25QU256C XM25QH64C XM25QH128C XM25QH256C TEST=test Signed-off-by: Luke He <sixuerain(a)qq.com> Change-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969 Change-Id: I71e1ba0d739f080dd3030108d50da7667f75ced0 --- M flashchips.c M flashchips.h 2 files changed, 245 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/10/49010/1 diff --git a/flashchips.c b/flashchips.c index c4a1e6f..3e27e79 100644 --- a/flashchips.c +++ b/flashchips.c @@ -18993,6 +18993,244 @@ }, { + .vendor = "XMC", + .name = "XM25QH64C", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QH64C, + .total_size = 8192, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "XMC", + .name = "XM25QU64C", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QU64C, + .total_size = 8192, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "XMC", + .name = "XM25QH128C", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QH128C, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "XMC", + .name = "XM25QU128C", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QU128C, + .total_size = 16384, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "XMC", + .name = "XM25QH256C", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QH256C, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN + | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "XMC", + .name = "XM25QU256C", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QU256C, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN + | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { .vendor = "Zetta Device", .name = "ZD25D20", .bustype = BUS_SPI, diff --git a/flashchips.h b/flashchips.h index 394eb30..a85fa6a 100644 --- a/flashchips.h +++ b/flashchips.h @@ -792,7 +792,7 @@ * ST25P chips are SPI, first byte of device ID is memory type, second * byte of device ID is related to log(bitsize) at least for some chips. */ -#define ST_ID 0x20 /* ST / SGS/Thomson / Numonyx (later acquired by Micron) */ +#define ST_ID 0x20 /* ST / SGS/Thomson / Numonyx / XMC(later acquired by Micron) */ #define ST_M25P05A 0x2010 #define ST_M25P05_RES 0x05 #define ST_M25P10A 0x2011 @@ -811,6 +811,12 @@ #define ST_M45PE40 0x4013 #define ST_M45PE80 0x4014 #define ST_M45PE16 0x4015 +#define XMC_XM25QH64C 0x4017 +#define XMC_XM25QU64C 0x4117 +#define XMC_XM25QH128C 0x4018 +#define XMC_XM25QU128C 0x4118 +#define XMC_XM25QH256C 0x4019 +#define XMC_XM25QU256C 0x4119 #define ST_M25PX80 0x7114 #define ST_M25PX16 0x7115 #define ST_M25PX32 0x7116 -- To view, visit https://review.coreboot.org/c/flashrom/+/49010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I71e1ba0d739f080dd3030108d50da7667f75ced0 Gerrit-Change-Number: 49010 Gerrit-PatchSet: 1 Gerrit-Owner: luke <sixuerain(a)qq.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips.c: Add support for XMC new spi flash types
by luke (Code Review) 29 Dec '20

29 Dec '20

Hello build bot (Jenkins), Edward O'Callaghan, Angel Pons, Nikolai Artemiev, Carl-Daniel Hailfinger, Uwe Hermann, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/48949 to look at the new patch set (#2). Change subject: flashchips.c: Add support for XMC new spi flash types ...................................................................... flashchips.c: Add support for XMC new spi flash types XM25QU64C XM25QU128C XM25QU256C XM25QH64C XM25QH128C XM25QH256C Signed-off-by: Luke He <sixuerain(a)qq.com> Change-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969 --- M flashchips.c M flashchips.h 2 files changed, 245 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/49/48949/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/48949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969 Gerrit-Change-Number: 48949 Gerrit-PatchSet: 2 Gerrit-Owner: luke <sixuerain(a)qq.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Carl-Daniel Hailfinger <hailfinger(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Uwe Hermann <uwe(a)hermann-uwe.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: flashchips.c: Add support for XMC new spi flash types
by luke (Code Review) 29 Dec '20

29 Dec '20

luke has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/49009 ) Change subject: flashchips.c: Add support for XMC new spi flash types ...................................................................... flashchips.c: Add support for XMC new spi flash types XM25QU64C XM25QU128C XM25QU256C XM25QH64C XM25QH128C XM25QH256C TEST=test Signed-off-by: Luke He <sixuerain(a)qq.com> Change-Id: Id16199b7c2fd39961f4e6d80138dcbc504f649bf --- M flashchips.c M flashchips.h 2 files changed, 245 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/09/49009/1 diff --git a/flashchips.c b/flashchips.c index c4a1e6f..3e27e79 100644 --- a/flashchips.c +++ b/flashchips.c @@ -18993,6 +18993,244 @@ }, { + .vendor = "XMC", + .name = "XM25QH64C", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QH64C, + .total_size = 8192, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "XMC", + .name = "XM25QU64C", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QU64C, + .total_size = 8192, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "XMC", + .name = "XM25QH128C", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QH128C, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "XMC", + .name = "XM25QU128C", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QU128C, + .total_size = 16384, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "XMC", + .name = "XM25QH256C", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QH256C, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN + | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "XMC", + .name = "XM25QU256C", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = XMC_XM25QU256C, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN + | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { .vendor = "Zetta Device", .name = "ZD25D20", .bustype = BUS_SPI, diff --git a/flashchips.h b/flashchips.h index 394eb30..a85fa6a 100644 --- a/flashchips.h +++ b/flashchips.h @@ -792,7 +792,7 @@ * ST25P chips are SPI, first byte of device ID is memory type, second * byte of device ID is related to log(bitsize) at least for some chips. */ -#define ST_ID 0x20 /* ST / SGS/Thomson / Numonyx (later acquired by Micron) */ +#define ST_ID 0x20 /* ST / SGS/Thomson / Numonyx / XMC(later acquired by Micron) */ #define ST_M25P05A 0x2010 #define ST_M25P05_RES 0x05 #define ST_M25P10A 0x2011 @@ -811,6 +811,12 @@ #define ST_M45PE40 0x4013 #define ST_M45PE80 0x4014 #define ST_M45PE16 0x4015 +#define XMC_XM25QH64C 0x4017 +#define XMC_XM25QU64C 0x4117 +#define XMC_XM25QH128C 0x4018 +#define XMC_XM25QU128C 0x4118 +#define XMC_XM25QH256C 0x4019 +#define XMC_XM25QU256C 0x4119 #define ST_M25PX80 0x7114 #define ST_M25PX16 0x7115 #define ST_M25PX32 0x7116 -- To view, visit https://review.coreboot.org/c/flashrom/+/49009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id16199b7c2fd39961f4e6d80138dcbc504f649bf Gerrit-Change-Number: 49009 Gerrit-PatchSet: 1 Gerrit-Owner: luke <sixuerain(a)qq.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips.c: Add support for XMC new spi flash types
by Edward O'Callaghan (Code Review) 29 Dec '20

29 Dec '20

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/48949 ) Change subject: flashchips.c: Add support for XMC new spi flash types ...................................................................... Patch Set 1: Code-Review+1 (8 comments) Thank you for the patch. Please see comments inline for some minor issues. https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.h File flashchips.h: https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.h@814 PS1, Line 814: two tabs needed to line up with the rest from the looks of it. https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.c File flashchips.c: https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.c@18994 PS1, Line 18994: spurious tab, delete. https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.c@19004 PS1, Line 19004: TEST_OK_PREW Were these all tested? if not then you want `TEST_UNTESTED`. The meaning of these are defined in flash.h just for your information. If they were indeed tested please update the commit message with a TEST=test ran line to indicate how. https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.c@19070 PS1, Line 19070: spurious tab, delete. https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.c@19148 PS1, Line 19148: spurious tab, delete. https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.c@19149 PS1, Line 19149: { too many braces, delete this one. https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.c@19150 PS1, Line 19150: spurious tab, delete. https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.c@19192 PS1, Line 19192: spurious tab, delete. -- To view, visit https://review.coreboot.org/c/flashrom/+/48949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969 Gerrit-Change-Number: 48949 Gerrit-PatchSet: 1 Gerrit-Owner: Luke He <sixuerain(a)qq.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Carl-Daniel Hailfinger <hailfinger(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Uwe Hermann <uwe(a)hermann-uwe.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 Dec 2020 03:59:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: realtek_mst_i2c_spi.c: Update PAGE_SIZE and fix write
by Shiyu Sun (Code Review) 28 Dec '20

28 Dec '20

Shiyu Sun has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48840 ) Change subject: realtek_mst_i2c_spi.c: Update PAGE_SIZE and fix write ...................................................................... realtek_mst_i2c_spi.c: Update PAGE_SIZE and fix write Update the PAGE_SIZE to 128 as fix r/w on different devices, also fix the write page mapping for it. BUG=b:147402710 TEST=build and run flashrom to read&write on multiple devices Signed-off-by: Shiyu Sun <sshiyu(a)chromium.org> Change-Id: Ifcdd3548519eb37440e67fcf6206279cff05b159 --- M Makefile M realtek_mst_i2c_spi.c 2 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/40/48840/1 diff --git a/Makefile b/Makefile index 0498624..a79bb82 100644 --- a/Makefile +++ b/Makefile @@ -737,10 +737,10 @@ CONFIG_STLINKV3_SPI ?= yes # Disables LSPCON support until the i2c helper supports multiple systems. -CONFIG_LSPCON_I2C_SPI ?= no +CONFIG_LSPCON_I2C_SPI ?= yes # Disables REALTEK_MST support until the i2c helper supports multiple systems. -CONFIG_REALTEK_MST_I2C_SPI ?= no +CONFIG_REALTEK_MST_I2C_SPI ?= yes # Always enable dummy tracing for now. CONFIG_DUMMY ?= yes diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 80caf86..dabec70 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -28,7 +28,7 @@ #define MCU_I2C_SLAVE_ADDR 0x94 #define REGISTER_ADDRESS (0x94 >> 1) -#define PAGE_SIZE 256 +#define PAGE_SIZE 128 #define MAX_SPI_WAIT_RETRIES 1000 #define MCU_MODE 0x6F @@ -386,7 +386,8 @@ ret |= realtek_mst_i2c_spi_write_register(fd, 0x71, page_len-1); uint8_t block_idx = (start + i) >> 16; uint8_t page_idx = (start + i) >> 8; - ret |= realtek_mst_i2c_spi_map_page(fd, block_idx, page_idx, 0); + uint8_t byte_idx = start + i; + ret |= realtek_mst_i2c_spi_map_page(fd, block_idx, page_idx, byte_idx); if (ret) break; -- To view, visit https://review.coreboot.org/c/flashrom/+/48840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ifcdd3548519eb37440e67fcf6206279cff05b159 Gerrit-Change-Number: 48840 Gerrit-PatchSet: 1 Gerrit-Owner: Shiyu Sun <sshiyu(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips.c: Add support for XMC new spi flash types
by Luke He (Code Review) 28 Dec '20

28 Dec '20

Luke He has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/48949 ) Change subject: flashchips.c: Add support for XMC new spi flash types ...................................................................... Patch Set 1: this patch is for XMC new spi flash -- To view, visit https://review.coreboot.org/c/flashrom/+/48949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969 Gerrit-Change-Number: 48949 Gerrit-PatchSet: 1 Gerrit-Owner: Luke He <sixuerain(a)qq.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Carl-Daniel Hailfinger <hailfinger(a)gmail.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Uwe Hermann <uwe(a)hermann-uwe.de> Gerrit-Comment-Date: Mon, 28 Dec 2020 12:14:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: Add missing platform.h includes
by Miriam Polzer (Code Review) 26 Dec '20

26 Dec '20

Miriam Polzer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48880 ) Change subject: Add missing platform.h includes ...................................................................... Add missing platform.h includes Include platform.h in all files using its macros. BUG=none TEST=builds Signed-off-by: Miriam Polzer <mpolzer(a)google.com> Change-Id: If17a3d58c02222f61b4e0335879eeed1638b583c --- M ch341a_spi.c M internal.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/80/48880/1 diff --git a/ch341a_spi.c b/ch341a_spi.c index 17c37eb..84cc3fe 100644 --- a/ch341a_spi.c +++ b/ch341a_spi.c @@ -20,6 +20,7 @@ #include <string.h> #include <libusb.h> #include "flash.h" +#include "platform.h" #include "programmer.h" /* LIBUSB_CALL ensures the right calling conventions on libusb callbacks. diff --git a/internal.c b/internal.c index 4390b45..bdbe32d 100644 --- a/internal.c +++ b/internal.c @@ -18,6 +18,7 @@ #include <string.h> #include <stdlib.h> #include "flash.h" +#include "platform.h" #include "programmer.h" #include "hwaccess.h" -- To view, visit https://review.coreboot.org/c/flashrom/+/48880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If17a3d58c02222f61b4e0335879eeed1638b583c Gerrit-Change-Number: 48880 Gerrit-PatchSet: 1 Gerrit-Owner: Miriam Polzer <mpolzer(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: sb600spi.c: Fix for 0x790b rev 0x61
by Edward O'Callaghan (Code Review) 23 Dec '20

23 Dec '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44073 ) Change subject: sb600spi.c: Fix for 0x790b rev 0x61 ...................................................................... sb600spi.c: Fix for 0x790b rev 0x61 Adds support for rev 0x61 of pid 0x790b. Note that the read callback requires a memory mapping. Change-Id: I5ce63b5de863aed0442cb4ffeff981e9b2fa445b Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M sb600spi.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/44073/1 diff --git a/sb600spi.c b/sb600spi.c index 5892d57..d879281 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -76,7 +76,7 @@ .max_data_write = FIFO_SIZE_YANGTZE - 3, .command = spi100_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = default_spi_read, + .read = read_memmapped, .write_256 = default_spi_write_256, .write_aai = default_spi_write_aai, }; @@ -143,7 +143,7 @@ if (rev == 0x4a) { amd_gen = CHIPSET_YANGTZE; msg_pdbg("Yangtze detected.\n"); - } else if (rev == 0x4b) { + } else if (rev == 0x4b || rev == 0x61) { amd_gen = CHIPSET_PROMONTORY; msg_pdbg("Promontory detected.\n"); } else { -- To view, visit https://review.coreboot.org/c/flashrom/+/44073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5ce63b5de863aed0442cb4ffeff981e9b2fa445b Gerrit-Change-Number: 44073 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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