December 2020 - flashrom-gerrit

Change in flashrom[master]: realtek_mst_i2c_spi.c: Add ISP mode check
by Shiyu Sun (Code Review) 23 Dec '20

23 Dec '20

Shiyu Sun has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48662 ) Change subject: realtek_mst_i2c_spi.c: Add ISP mode check ...................................................................... realtek_mst_i2c_spi.c: Add ISP mode check Check ISP mode before doing reset and add waiting after the enter ISP mode command. BUG=None TEST=build and run mst commands Signed-off-by: Shiyu Sun <sshiyu(a)chromium.org> Change-Id: Ib1ab8370eb6335a77bb293fc98a8ab7be465db4f --- M realtek_mst_i2c_spi.c 1 file changed, 27 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/62/48662/1 diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 538b07a..0126157 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -32,7 +32,7 @@ #define MAX_SPI_WAIT_RETRIES 1000 #define MCU_MODE 0x6F -#define ENTER_ISP_MODE 0x80 +#define MCU_ISP_MODE_MASK 0x80 #define START_WRITE_XFER 0xA0 #define WRITE_XFER_STATUS_MASK 0x20 @@ -117,10 +117,30 @@ return (val & mask) != target ? SPI_GENERIC_ERROR : ret; } +static int realtek_mst_i2c_spi_in_isp_mode(int fd) +{ + uint8_t mcu_mode_val; + int ret = realtek_mst_i2c_spi_read_register(fd, MCU_MODE, &mcu_mode_val); + if (ret || (mcu_mode_val & MCU_ISP_MODE_MASK) == 0) + return 0; + return 1; +} + static int realtek_mst_i2c_spi_enter_isp_mode(int fd) { - int ret = realtek_mst_i2c_spi_write_register(fd, MCU_MODE, ENTER_ISP_MODE); + int ret = realtek_mst_i2c_spi_write_register(fd, MCU_MODE, MCU_ISP_MODE_MASK); + /* wait for isp enter */ + int retry = 10; + while (retry-- > 0) { + if (realtek_mst_i2c_spi_in_isp_mode(fd) == 1) + break; + struct timespec wait_200ms = { 0, (unsigned)2e8 }; + nanosleep(&wait_200ms, NULL); + } + + if (retry < 0) + return SPI_GENERIC_ERROR; // set internal osc divider register to default to speed up MCU // 0x06A0 = 0x74 ret |= realtek_mst_i2c_spi_write_register(fd, 0xF4, 0x9F); @@ -140,6 +160,11 @@ static int realtek_mst_i2c_spi_reset_mpu(int fd) { + if (realtek_mst_i2c_spi_in_isp_mode(fd) == 0) { + msg_perr("%s: MST not in ISP mode, reset will not happen.\n", __func__); + return SPI_GENERIC_ERROR; + } + int ret = 0; // 0xFFEE[1] = 1; uint8_t val = 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/48662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib1ab8370eb6335a77bb293fc98a8ab7be465db4f Gerrit-Change-Number: 48662 Gerrit-PatchSet: 1 Gerrit-Owner: Shiyu Sun <sshiyu(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: sb600spi.c: Detect rev 0x51 as Promontory
by Edward O'Callaghan (Code Review) 23 Dec '20

23 Dec '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48779 ) Change subject: sb600spi.c: Detect rev 0x51 as Promontory ...................................................................... sb600spi.c: Detect rev 0x51 as Promontory As reported on the mailing list. Change-Id: Iff8340633021fde1dc32572ab5f5da85df5d9048 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M sb600spi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/48779/1 diff --git a/sb600spi.c b/sb600spi.c index 2e27cee..ef9da4b 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -129,7 +129,7 @@ * The revisions I have found by searching various lspci * outputs are as follows: 0x4b, 0x59 & 0x61. */ - } else if (rev == 0x4b || rev == 0x59 || rev == 0x61) { + } else if (rev == 0x4b || rev == 0x51 || rev == 0x59 || rev == 0x61) { msg_pdbg("Promontory (rev 0x%02x) detected.\n", rev); return CHIPSET_PROMONTORY; } else { -- To view, visit https://review.coreboot.org/c/flashrom/+/48779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iff8340633021fde1dc32572ab5f5da85df5d9048 Gerrit-Change-Number: 48779 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: chipdrivers.h: Trivial fix style of write_28sf040() signature
by Edward O'Callaghan (Code Review) 21 Dec '20

21 Dec '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48744 ) Change subject: chipdrivers.h: Trivial fix style of write_28sf040() signature ...................................................................... chipdrivers.h: Trivial fix style of write_28sf040() signature This is correct on the Chromium side so fix the missing space here. Change-Id: I9dd27a4d8a1b87ce96b2a3f8cbe80f40c79b0354 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M chipdrivers.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/44/48744/1 diff --git a/chipdrivers.h b/chipdrivers.h index b42c363..e1d6aa9 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -159,7 +159,7 @@ /* sst28sf040.c */ int erase_chip_28sf040(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int erase_sector_28sf040(struct flashctx *flash, unsigned int address, unsigned int sector_size); -int write_28sf040(struct flashctx *flash, const uint8_t *buf,unsigned int start, unsigned int len); +int write_28sf040(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int unprotect_28sf040(struct flashctx *flash); int protect_28sf040(struct flashctx *flash); -- To view, visit https://review.coreboot.org/c/flashrom/+/48744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9dd27a4d8a1b87ce96b2a3f8cbe80f40c79b0354 Gerrit-Change-Number: 48744 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: layout.h,c: Use 'false' over '0' for bool type
by Edward O'Callaghan (Code Review) 21 Dec '20

21 Dec '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48743 ) Change subject: layout.h,c: Use 'false' over '0' for bool type ...................................................................... layout.h,c: Use 'false' over '0' for bool type The field member 'included' is of type boolean and so keep to using 'true, false' values over numerics like '0'. Get rid of a unnecessary yet trivial tab at the end of layout.h while we are here. BUG=none BRANCH=none TEST=builds Change-Id: Ib594de2834175482ae5e36d9dd354ef2555c53d5 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M layout.c M layout.h 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/43/48743/1 diff --git a/layout.c b/layout.c index d80b01f..272912c 100644 --- a/layout.c +++ b/layout.c @@ -81,7 +81,7 @@ } layout->entries[layout->num_entries].start = strtol(tstr1, (char **)NULL, 16); layout->entries[layout->num_entries].end = strtol(tstr2, (char **)NULL, 16); - layout->entries[layout->num_entries].included = 0; + layout->entries[layout->num_entries].included = false; layout->entries[layout->num_entries].name = strdup(tempname); if (!layout->entries[layout->num_entries].name) { msg_gerr("Error adding layout entry: %s\n", strerror(errno)); @@ -205,7 +205,7 @@ for (i = 0; i < layout->num_entries; i++) { free(layout->entries[i].name); - layout->entries[i].included = 0; + layout->entries[i].included = false; } layout->num_entries = 0; } diff --git a/layout.h b/layout.h index 8e4eb13..cceedd1 100644 --- a/layout.h +++ b/layout.h @@ -67,4 +67,4 @@ const struct romentry *layout_next_included_region(const struct flashrom_layout *, chipoff_t); const struct romentry *layout_next_included(const struct flashrom_layout *, const struct romentry *); -#endif /* !__LAYOUT_H__ */ +#endif /* !__LAYOUT_H__ */ -- To view, visit https://review.coreboot.org/c/flashrom/+/48743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib594de2834175482ae5e36d9dd354ef2555c53d5 Gerrit-Change-Number: 48743 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: chipset_enable.c: Mark Intel H110 as DEP
by Angel Pons (Code Review) 18 Dec '20

18 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48384 ) Change subject: chipset_enable.c: Mark Intel H110 as DEP ...................................................................... chipset_enable.c: Mark Intel H110 as DEP Tested reading, writing and erasing the internal flash chip using an HP 280 G2 SFF mainboard with an Intel H110 PCH. However, since ME-enabled chipsets are marked as DEP instead of OK, this one shall also be. Change-Id: I5deac6e43a43ee9748aaa7dadae50065613488b1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/84/48384/1 diff --git a/chipset_enable.c b/chipset_enable.c index 7c98798..308935c 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2022,7 +2022,7 @@ {0x8086, 0x0284, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch400}, {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, - {0x8086, 0xa143, B_S, NT, "Intel", "H110", enable_flash_pch100}, + {0x8086, 0xa143, B_S, DEP, "Intel", "H110", enable_flash_pch100}, {0x8086, 0xa144, B_S, NT, "Intel", "H170", enable_flash_pch100}, {0x8086, 0xa145, B_S, NT, "Intel", "Z170", enable_flash_pch100}, {0x8086, 0xa146, B_S, NT, "Intel", "Q170", enable_flash_pch100}, -- To view, visit https://review.coreboot.org/c/flashrom/+/48384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5deac6e43a43ee9748aaa7dadae50065613488b1 Gerrit-Change-Number: 48384 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: dediprog.c: Fix segmentation fault on no device found
by Medicine Yeh (Code Review) 17 Dec '20

17 Dec '20

Medicine Yeh has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48688 ) Change subject: dediprog.c: Fix segmentation fault on no device found ...................................................................... dediprog.c: Fix segmentation fault on no device found libusb_exit() call is done by dediprog_open() under the ret == 1 condition. Removing this line has no impact on any flow and side effect of the program. Change-Id: I38b3f3ee3f9d46845df1404791f4a4782320aa7c Signed-off-by: Medicine Yeh <medicinehy(a)gmail.com> --- M dediprog.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/48688/1 diff --git a/dediprog.c b/dediprog.c index a9d0034..c50e374 100644 --- a/dediprog.c +++ b/dediprog.c @@ -1188,7 +1188,6 @@ ret = dediprog_open(i); if (ret == -1) { /* no dev */ - libusb_exit(usb_ctx); return 1; } else if (ret == -2) { /* busy dev */ -- To view, visit https://review.coreboot.org/c/flashrom/+/48688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I38b3f3ee3f9d46845df1404791f4a4782320aa7c Gerrit-Change-Number: 48688 Gerrit-PatchSet: 1 Gerrit-Owner: Medicine Yeh <medicinehy(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: chipset_enable.c: Remove futile attempt to disable lock
by Andy Pont (Code Review) 15 Dec '20

15 Dec '20

Andy Pont has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48643 ) Change subject: chipset_enable.c: Remove futile attempt to disable lock ...................................................................... chipset_enable.c: Remove futile attempt to disable lock For all recent Intel chipsets (and possibly others) the ability to disable the lock fails. This leads to confusing messages being presented to the user where unlocking fails but the flash update process works correctly. Remove the unlock attempt which had alreayd been marked in the source code comments as "futile". Signed-off-by: Andy Pont <andy.pont(a)sdcsystems.com> Change-Id: Id70e132f8feb7b91cbf79d8cdf07744f8763e11b --- M chipset_enable.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/43/48643/1 diff --git a/chipset_enable.c b/chipset_enable.c index 9205d0e..3ca6ba8 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -333,7 +333,6 @@ wanted |= (1 << 2); wanted |= (1 << 0); /* Set BIOS Write Enable */ - wanted &= ~(1 << 1); /* Disable lock (futile) */ /* Only write the register if it's necessary */ if (wanted != old) { -- To view, visit https://review.coreboot.org/c/flashrom/+/48643 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id70e132f8feb7b91cbf79d8cdf07744f8763e11b Gerrit-Change-Number: 48643 Gerrit-PatchSet: 1 Gerrit-Owner: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: chipset_enable.c: change "Broadwell U Base" NT->OK
by Nikolai Artemiev (Code Review) 14 Dec '20

14 Dec '20

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47218 ) Change subject: chipset_enable.c: change "Broadwell U Base" NT->OK ...................................................................... chipset_enable.c: change "Broadwell U Base" NT->OK Change-Id: I0b4d1dd2b271537faea15856442fe183d9de3318 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/47218/1 diff --git a/chipset_enable.c b/chipset_enable.c index 4273478..77d07a1 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1997,7 +1997,7 @@ {0x8086, 0x9cc1, B_FS, NT, "Intel", "Haswell U Sample", enable_flash_pch9_lp}, {0x8086, 0x9cc2, B_FS, NT, "Intel", "Broadwell U Sample", enable_flash_pch9_lp}, {0x8086, 0x9cc3, B_FS, DEP, "Intel", "Broadwell U Premium", enable_flash_pch9_lp}, - {0x8086, 0x9cc5, B_FS, NT, "Intel", "Broadwell U Base", enable_flash_pch9_lp}, + {0x8086, 0x9cc5, B_FS, OK, "Intel", "Broadwell U Base", enable_flash_pch9_lp}, {0x8086, 0x9cc6, B_FS, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9_lp}, {0x8086, 0x9cc7, B_FS, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp}, {0x8086, 0x9cc9, B_FS, NT, "Intel", "Broadwell Y Base", enable_flash_pch9_lp}, -- To view, visit https://review.coreboot.org/c/flashrom/+/47218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I0b4d1dd2b271537faea15856442fe183d9de3318 Gerrit-Change-Number: 47218 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips.c: Add Sanyo LF25FW203A entry
by Nikolai Artemiev (Code Review) 13 Dec '20

13 Dec '20

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48443 ) Change subject: flashchips.c: Add Sanyo LF25FW203A entry ...................................................................... flashchips.c: Add Sanyo LF25FW203A entry Chip imported from cros flashrom at `commit e50562c68fc4901acb6243b4f4d2c182a162ad41` Change-Id: I530e123e49d50b032496f18efce438e9ad7e7552 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M flashchips.c 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/43/48443/1 diff --git a/flashchips.c b/flashchips.c index bc5de4a..76b530a 100644 --- a/flashchips.c +++ b/flashchips.c @@ -15659,6 +15659,32 @@ }, { + .vendor = "Sanyo", + .name = "LF25FW203A", + .bustype = BUS_SPI, + .manufacture_id = SANYO_ID, + .model_id = SANYO_LE25FW203A, + .total_size = 2048, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { .vendor = "Sharp", .name = "LH28F008BJT-BTLZ1", .bustype = BUS_PARALLEL, -- To view, visit https://review.coreboot.org/c/flashrom/+/48443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I530e123e49d50b032496f18efce438e9ad7e7552 Gerrit-Change-Number: 48443 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: meson: Add missing config option for J-Link SPI
by zapb (Code Review) 13 Dec '20

13 Dec '20

zapb has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48478 ) Change subject: meson: Add missing config option for J-Link SPI ...................................................................... meson: Add missing config option for J-Link SPI Signed-off-by: Marc Schink <dev(a)zapb.de> Change-Id: I476c649f9db7342688560aac9ee5df056517a028 --- M meson.build M meson_options.txt 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/48478/1 diff --git a/meson.build b/meson.build index fd5a5ef..556183e 100644 --- a/meson.build +++ b/meson.build @@ -38,6 +38,7 @@ config_dediprog = get_option('config_dediprog') config_developerbox_spi = get_option('config_developerbox_spi') config_digilent_spi = get_option('config_digilent_spi') +config_jlink_spi = get_option('config_jlink_spi') config_drkaiser = get_option('config_drkaiser') config_dummy = get_option('config_dummy') config_ene_lpc = get_option('config_ene_lpc') @@ -159,6 +160,11 @@ srcs += 'digilent_spi.c' cargs += '-DCONFIG_DIGILENT_SPI=1' endif +if config_jlink_spi + srcs += 'jlink_spi.c' + cargs += '-DCONFIG_JLINK_SPI=1' + deps += dependency('libjaylink') +endif if config_drkaiser srcs += 'drkaiser.c' cargs += '-DCONFIG_DRKAISER=1' diff --git a/meson_options.txt b/meson_options.txt index 9c0a798..89fcbee 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -9,6 +9,7 @@ option('config_dediprog', type : 'boolean', value : true, description : 'Dediprog SF100') option('config_developerbox_spi', type : 'boolean', value : true, description : 'Developerbox emergency recovery') option('config_digilent_spi', type : 'boolean', value : true, description : 'Digilent Development board JTAG') +option('config_jlink_spi', type : 'boolean', value : false, description : 'SEGGER J-Link and compatible devices') option('config_drkaiser', type : 'boolean', value : true, description : 'Dr. Kaiser') option('config_dummy', type : 'boolean', value : true, description : 'dummy tracing') option('config_ene_lpc', type : 'boolean', value : true, description : 'ENE LPC interface keyboard controller') -- To view, visit https://review.coreboot.org/c/flashrom/+/48478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I476c649f9db7342688560aac9ee5df056517a028 Gerrit-Change-Number: 48478 Gerrit-PatchSet: 1 Gerrit-Owner: zapb <dev(a)zapb.de> Gerrit-MessageType: newchange

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flashrom-gerrit December 2020