December 2020 - flashrom-gerrit

Change in flashrom[master]: flashchips.c: Add support for XMC new spi flash types
by Edward O'Callaghan (Code Review) 30 Dec '20

30 Dec '20

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/48949 ) Change subject: flashchips.c: Add support for XMC new spi flash types ...................................................................... Patch Set 1: Code-Review+1 (8 comments) Thank you for the patch. Please see comments inline for some minor issues. https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.h File flashchips.h: https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.h@814 PS1, Line 814: two tabs needed to line up with the rest from the looks of it. https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.c File flashchips.c: https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.c@18994 PS1, Line 18994: spurious tab, delete. https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.c@19004 PS1, Line 19004: TEST_OK_PREW Were these all tested? if not then you want `TEST_UNTESTED`. The meaning of these are defined in flash.h just for your information. If they were indeed tested please update the commit message with a TEST=test ran line to indicate how. https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.c@19070 PS1, Line 19070: spurious tab, delete. https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.c@19148 PS1, Line 19148: spurious tab, delete. https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.c@19149 PS1, Line 19149: { too many braces, delete this one. https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.c@19150 PS1, Line 19150: spurious tab, delete. https://review.coreboot.org/c/flashrom/+/48949/1/flashchips.c@19192 PS1, Line 19192: spurious tab, delete. -- To view, visit https://review.coreboot.org/c/flashrom/+/48949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969 Gerrit-Change-Number: 48949 Gerrit-PatchSet: 1 Gerrit-Owner: Luke He <sixuerain(a)qq.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Carl-Daniel Hailfinger <hailfinger(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Uwe Hermann <uwe(a)hermann-uwe.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 Dec 2020 03:59:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: realtek_mst_i2c_spi.c: Update PAGE_SIZE and fix write
by Shiyu Sun (Code Review) 29 Dec '20

29 Dec '20

Shiyu Sun has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48840 ) Change subject: realtek_mst_i2c_spi.c: Update PAGE_SIZE and fix write ...................................................................... realtek_mst_i2c_spi.c: Update PAGE_SIZE and fix write Update the PAGE_SIZE to 128 as fix r/w on different devices, also fix the write page mapping for it. BUG=b:147402710 TEST=build and run flashrom to read&write on multiple devices Signed-off-by: Shiyu Sun <sshiyu(a)chromium.org> Change-Id: Ifcdd3548519eb37440e67fcf6206279cff05b159 --- M Makefile M realtek_mst_i2c_spi.c 2 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/40/48840/1 diff --git a/Makefile b/Makefile index 0498624..a79bb82 100644 --- a/Makefile +++ b/Makefile @@ -737,10 +737,10 @@ CONFIG_STLINKV3_SPI ?= yes # Disables LSPCON support until the i2c helper supports multiple systems. -CONFIG_LSPCON_I2C_SPI ?= no +CONFIG_LSPCON_I2C_SPI ?= yes # Disables REALTEK_MST support until the i2c helper supports multiple systems. -CONFIG_REALTEK_MST_I2C_SPI ?= no +CONFIG_REALTEK_MST_I2C_SPI ?= yes # Always enable dummy tracing for now. CONFIG_DUMMY ?= yes diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 80caf86..dabec70 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -28,7 +28,7 @@ #define MCU_I2C_SLAVE_ADDR 0x94 #define REGISTER_ADDRESS (0x94 >> 1) -#define PAGE_SIZE 256 +#define PAGE_SIZE 128 #define MAX_SPI_WAIT_RETRIES 1000 #define MCU_MODE 0x6F @@ -386,7 +386,8 @@ ret |= realtek_mst_i2c_spi_write_register(fd, 0x71, page_len-1); uint8_t block_idx = (start + i) >> 16; uint8_t page_idx = (start + i) >> 8; - ret |= realtek_mst_i2c_spi_map_page(fd, block_idx, page_idx, 0); + uint8_t byte_idx = start + i; + ret |= realtek_mst_i2c_spi_map_page(fd, block_idx, page_idx, byte_idx); if (ret) break; -- To view, visit https://review.coreboot.org/c/flashrom/+/48840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ifcdd3548519eb37440e67fcf6206279cff05b159 Gerrit-Change-Number: 48840 Gerrit-PatchSet: 1 Gerrit-Owner: Shiyu Sun <sshiyu(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips.c: Add support for XMC new spi flash types
by Luke He (Code Review) 28 Dec '20

28 Dec '20

Luke He has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/48949 ) Change subject: flashchips.c: Add support for XMC new spi flash types ...................................................................... Patch Set 1: this patch is for XMC new spi flash -- To view, visit https://review.coreboot.org/c/flashrom/+/48949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969 Gerrit-Change-Number: 48949 Gerrit-PatchSet: 1 Gerrit-Owner: Luke He <sixuerain(a)qq.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Carl-Daniel Hailfinger <hailfinger(a)gmail.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Uwe Hermann <uwe(a)hermann-uwe.de> Gerrit-Comment-Date: Mon, 28 Dec 2020 12:14:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: Add missing platform.h includes
by Miriam Polzer (Code Review) 26 Dec '20

26 Dec '20

Miriam Polzer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48880 ) Change subject: Add missing platform.h includes ...................................................................... Add missing platform.h includes Include platform.h in all files using its macros. BUG=none TEST=builds Signed-off-by: Miriam Polzer <mpolzer(a)google.com> Change-Id: If17a3d58c02222f61b4e0335879eeed1638b583c --- M ch341a_spi.c M internal.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/80/48880/1 diff --git a/ch341a_spi.c b/ch341a_spi.c index 17c37eb..84cc3fe 100644 --- a/ch341a_spi.c +++ b/ch341a_spi.c @@ -20,6 +20,7 @@ #include <string.h> #include <libusb.h> #include "flash.h" +#include "platform.h" #include "programmer.h" /* LIBUSB_CALL ensures the right calling conventions on libusb callbacks. diff --git a/internal.c b/internal.c index 4390b45..bdbe32d 100644 --- a/internal.c +++ b/internal.c @@ -18,6 +18,7 @@ #include <string.h> #include <stdlib.h> #include "flash.h" +#include "platform.h" #include "programmer.h" #include "hwaccess.h" -- To view, visit https://review.coreboot.org/c/flashrom/+/48880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If17a3d58c02222f61b4e0335879eeed1638b583c Gerrit-Change-Number: 48880 Gerrit-PatchSet: 1 Gerrit-Owner: Miriam Polzer <mpolzer(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: sb600spi.c: Fix for 0x790b rev 0x61
by Edward O'Callaghan (Code Review) 23 Dec '20

23 Dec '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44073 ) Change subject: sb600spi.c: Fix for 0x790b rev 0x61 ...................................................................... sb600spi.c: Fix for 0x790b rev 0x61 Adds support for rev 0x61 of pid 0x790b. Note that the read callback requires a memory mapping. Change-Id: I5ce63b5de863aed0442cb4ffeff981e9b2fa445b Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M sb600spi.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/44073/1 diff --git a/sb600spi.c b/sb600spi.c index 5892d57..d879281 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -76,7 +76,7 @@ .max_data_write = FIFO_SIZE_YANGTZE - 3, .command = spi100_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = default_spi_read, + .read = read_memmapped, .write_256 = default_spi_write_256, .write_aai = default_spi_write_aai, }; @@ -143,7 +143,7 @@ if (rev == 0x4a) { amd_gen = CHIPSET_YANGTZE; msg_pdbg("Yangtze detected.\n"); - } else if (rev == 0x4b) { + } else if (rev == 0x4b || rev == 0x61) { amd_gen = CHIPSET_PROMONTORY; msg_pdbg("Promontory detected.\n"); } else { -- To view, visit https://review.coreboot.org/c/flashrom/+/44073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5ce63b5de863aed0442cb4ffeff981e9b2fa445b Gerrit-Change-Number: 44073 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: realtek_mst_i2c_spi.c: Add ISP mode check
by Shiyu Sun (Code Review) 23 Dec '20

23 Dec '20

Shiyu Sun has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48662 ) Change subject: realtek_mst_i2c_spi.c: Add ISP mode check ...................................................................... realtek_mst_i2c_spi.c: Add ISP mode check Check ISP mode before doing reset and add waiting after the enter ISP mode command. BUG=None TEST=build and run mst commands Signed-off-by: Shiyu Sun <sshiyu(a)chromium.org> Change-Id: Ib1ab8370eb6335a77bb293fc98a8ab7be465db4f --- M realtek_mst_i2c_spi.c 1 file changed, 27 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/62/48662/1 diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 538b07a..0126157 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -32,7 +32,7 @@ #define MAX_SPI_WAIT_RETRIES 1000 #define MCU_MODE 0x6F -#define ENTER_ISP_MODE 0x80 +#define MCU_ISP_MODE_MASK 0x80 #define START_WRITE_XFER 0xA0 #define WRITE_XFER_STATUS_MASK 0x20 @@ -117,10 +117,30 @@ return (val & mask) != target ? SPI_GENERIC_ERROR : ret; } +static int realtek_mst_i2c_spi_in_isp_mode(int fd) +{ + uint8_t mcu_mode_val; + int ret = realtek_mst_i2c_spi_read_register(fd, MCU_MODE, &mcu_mode_val); + if (ret || (mcu_mode_val & MCU_ISP_MODE_MASK) == 0) + return 0; + return 1; +} + static int realtek_mst_i2c_spi_enter_isp_mode(int fd) { - int ret = realtek_mst_i2c_spi_write_register(fd, MCU_MODE, ENTER_ISP_MODE); + int ret = realtek_mst_i2c_spi_write_register(fd, MCU_MODE, MCU_ISP_MODE_MASK); + /* wait for isp enter */ + int retry = 10; + while (retry-- > 0) { + if (realtek_mst_i2c_spi_in_isp_mode(fd) == 1) + break; + struct timespec wait_200ms = { 0, (unsigned)2e8 }; + nanosleep(&wait_200ms, NULL); + } + + if (retry < 0) + return SPI_GENERIC_ERROR; // set internal osc divider register to default to speed up MCU // 0x06A0 = 0x74 ret |= realtek_mst_i2c_spi_write_register(fd, 0xF4, 0x9F); @@ -140,6 +160,11 @@ static int realtek_mst_i2c_spi_reset_mpu(int fd) { + if (realtek_mst_i2c_spi_in_isp_mode(fd) == 0) { + msg_perr("%s: MST not in ISP mode, reset will not happen.\n", __func__); + return SPI_GENERIC_ERROR; + } + int ret = 0; // 0xFFEE[1] = 1; uint8_t val = 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/48662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib1ab8370eb6335a77bb293fc98a8ab7be465db4f Gerrit-Change-Number: 48662 Gerrit-PatchSet: 1 Gerrit-Owner: Shiyu Sun <sshiyu(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: sb600spi.c: Detect rev 0x51 as Promontory
by Edward O'Callaghan (Code Review) 23 Dec '20

23 Dec '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48779 ) Change subject: sb600spi.c: Detect rev 0x51 as Promontory ...................................................................... sb600spi.c: Detect rev 0x51 as Promontory As reported on the mailing list. Change-Id: Iff8340633021fde1dc32572ab5f5da85df5d9048 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M sb600spi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/48779/1 diff --git a/sb600spi.c b/sb600spi.c index 2e27cee..ef9da4b 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -129,7 +129,7 @@ * The revisions I have found by searching various lspci * outputs are as follows: 0x4b, 0x59 & 0x61. */ - } else if (rev == 0x4b || rev == 0x59 || rev == 0x61) { + } else if (rev == 0x4b || rev == 0x51 || rev == 0x59 || rev == 0x61) { msg_pdbg("Promontory (rev 0x%02x) detected.\n", rev); return CHIPSET_PROMONTORY; } else { -- To view, visit https://review.coreboot.org/c/flashrom/+/48779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iff8340633021fde1dc32572ab5f5da85df5d9048 Gerrit-Change-Number: 48779 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: chipdrivers.h: Trivial fix style of write_28sf040() signature
by Edward O'Callaghan (Code Review) 20 Dec '20

20 Dec '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48744 ) Change subject: chipdrivers.h: Trivial fix style of write_28sf040() signature ...................................................................... chipdrivers.h: Trivial fix style of write_28sf040() signature This is correct on the Chromium side so fix the missing space here. Change-Id: I9dd27a4d8a1b87ce96b2a3f8cbe80f40c79b0354 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M chipdrivers.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/44/48744/1 diff --git a/chipdrivers.h b/chipdrivers.h index b42c363..e1d6aa9 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -159,7 +159,7 @@ /* sst28sf040.c */ int erase_chip_28sf040(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int erase_sector_28sf040(struct flashctx *flash, unsigned int address, unsigned int sector_size); -int write_28sf040(struct flashctx *flash, const uint8_t *buf,unsigned int start, unsigned int len); +int write_28sf040(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int unprotect_28sf040(struct flashctx *flash); int protect_28sf040(struct flashctx *flash); -- To view, visit https://review.coreboot.org/c/flashrom/+/48744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9dd27a4d8a1b87ce96b2a3f8cbe80f40c79b0354 Gerrit-Change-Number: 48744 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: layout.h,c: Use 'false' over '0' for bool type
by Edward O'Callaghan (Code Review) 20 Dec '20

20 Dec '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48743 ) Change subject: layout.h,c: Use 'false' over '0' for bool type ...................................................................... layout.h,c: Use 'false' over '0' for bool type The field member 'included' is of type boolean and so keep to using 'true, false' values over numerics like '0'. Get rid of a unnecessary yet trivial tab at the end of layout.h while we are here. BUG=none BRANCH=none TEST=builds Change-Id: Ib594de2834175482ae5e36d9dd354ef2555c53d5 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M layout.c M layout.h 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/43/48743/1 diff --git a/layout.c b/layout.c index d80b01f..272912c 100644 --- a/layout.c +++ b/layout.c @@ -81,7 +81,7 @@ } layout->entries[layout->num_entries].start = strtol(tstr1, (char **)NULL, 16); layout->entries[layout->num_entries].end = strtol(tstr2, (char **)NULL, 16); - layout->entries[layout->num_entries].included = 0; + layout->entries[layout->num_entries].included = false; layout->entries[layout->num_entries].name = strdup(tempname); if (!layout->entries[layout->num_entries].name) { msg_gerr("Error adding layout entry: %s\n", strerror(errno)); @@ -205,7 +205,7 @@ for (i = 0; i < layout->num_entries; i++) { free(layout->entries[i].name); - layout->entries[i].included = 0; + layout->entries[i].included = false; } layout->num_entries = 0; } diff --git a/layout.h b/layout.h index 8e4eb13..cceedd1 100644 --- a/layout.h +++ b/layout.h @@ -67,4 +67,4 @@ const struct romentry *layout_next_included_region(const struct flashrom_layout *, chipoff_t); const struct romentry *layout_next_included(const struct flashrom_layout *, const struct romentry *); -#endif /* !__LAYOUT_H__ */ +#endif /* !__LAYOUT_H__ */ -- To view, visit https://review.coreboot.org/c/flashrom/+/48743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib594de2834175482ae5e36d9dd354ef2555c53d5 Gerrit-Change-Number: 48743 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: chipset_enable.c: Mark Intel H110 as DEP
by Angel Pons (Code Review) 18 Dec '20

18 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48384 ) Change subject: chipset_enable.c: Mark Intel H110 as DEP ...................................................................... chipset_enable.c: Mark Intel H110 as DEP Tested reading, writing and erasing the internal flash chip using an HP 280 G2 SFF mainboard with an Intel H110 PCH. However, since ME-enabled chipsets are marked as DEP instead of OK, this one shall also be. Change-Id: I5deac6e43a43ee9748aaa7dadae50065613488b1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/84/48384/1 diff --git a/chipset_enable.c b/chipset_enable.c index 7c98798..308935c 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2022,7 +2022,7 @@ {0x8086, 0x0284, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch400}, {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, - {0x8086, 0xa143, B_S, NT, "Intel", "H110", enable_flash_pch100}, + {0x8086, 0xa143, B_S, DEP, "Intel", "H110", enable_flash_pch100}, {0x8086, 0xa144, B_S, NT, "Intel", "H170", enable_flash_pch100}, {0x8086, 0xa145, B_S, NT, "Intel", "Z170", enable_flash_pch100}, {0x8086, 0xa146, B_S, NT, "Intel", "Q170", enable_flash_pch100}, -- To view, visit https://review.coreboot.org/c/flashrom/+/48384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5deac6e43a43ee9748aaa7dadae50065613488b1 Gerrit-Change-Number: 48384 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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flashrom-gerrit December 2020