December 2020 - flashrom-gerrit

Change in flashrom[master]: Simplifying the initialisation flow for it85spi
by Anastasia Klimchuk (Code Review) Jan. 21, 2021

Jan. 21, 2021

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48196 ) Change subject: Simplifying the initialisation flow for it85spi ...................................................................... Simplifying the initialisation flow for it85spi 1) Inlining it85xx_spi_common_init since it's only used once in it85xx_spi_init, after inlining ret value is not needed. 2) Creating it86_init_error section to ensure that data is freed if error happened in initialisaton flow. BUG=b:172876667 TEST=builds Change-Id: Iac1b4ae9c6f34c5265e729ae0a80024800c3c272 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M it85spi.c 1 file changed, 32 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/48196/1 diff --git a/it85spi.c b/it85spi.c index 6215515..52b09b1 100644 --- a/it85spi.c +++ b/it85spi.c @@ -289,11 +289,18 @@ .write_aai = default_spi_write_aai, }; -static int it85xx_spi_common_init(struct superio s) +int it85xx_spi_init(struct superio s) { chipaddr base; + struct it85spi_data *data; + msg_pdbg("%s():%d superio.vendor=0x%02x\n", __func__, __LINE__, s.vendor); - struct it85spi_data *data = calloc(1, sizeof(struct it85spi_data)); + if (!(internal_buses_supported & BUS_FWH)) { + msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__); + return 1; + } + + data = calloc(1, sizeof(struct it85spi_data)); if (!data) { msg_perr("Unable to allocate space for extra SPI master data.\n"); return SPI_GENERIC_ERROR; @@ -301,12 +308,8 @@ spi_master_it85xx.data = data; - msg_pdbg("%s():%d superio.vendor=0x%02x\n", __func__, __LINE__, - s.vendor); - if (register_shutdown(it85xx_shutdown, data)) { - free(data); - return 1; + goto it85spi_init_error; } #ifdef LPC_IO @@ -334,9 +337,9 @@ * Major TODO here, and it will be a lot of work. */ base = (chipaddr)physmap("it85 communication", 0xFFFFF000, 0x1000); - if (base == (chipaddr)ERROR_PTR) - free(data); - return 1; + if (base == (chipaddr)ERROR_PTR) { + goto it85spi_init_error; + } msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__, (unsigned int)base); @@ -344,37 +347,27 @@ data->ce_low = (unsigned char *)(base + 0xD00); /* 0xFFFFFD00 */ #endif + msg_pdbg("%s: internal_buses_supported=0x%x\n", __func__, + internal_buses_supported); + /* Check for FWH because IT85 listens to FWH cycles. + * FIXME: The big question is whether FWH cycles are necessary + * for communication even if LPC_IO is defined. + */ + if (internal_buses_supported & BUS_FWH) + msg_pdbg("Registering IT85 SPI.\n"); + /* FIXME: Really leave FWH enabled? We can't use this region + * anymore since accessing it would mess up IT85 communication. + * If we decide to disable FWH for this region, we should print + * a debug message about it. + */ + /* Set this as SPI controller. */ + register_spi_master(&spi_master_it85xx); + return 0; -} -int it85xx_spi_init(struct superio s) -{ - int ret; - - if (!(internal_buses_supported & BUS_FWH)) { - msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__); - return 1; - } - ret = it85xx_spi_common_init(s); - msg_pdbg("FWH: %s():%d ret=%d\n", __func__, __LINE__, ret); - if (!ret) { - msg_pdbg("%s: internal_buses_supported=0x%x\n", __func__, - internal_buses_supported); - /* Check for FWH because IT85 listens to FWH cycles. - * FIXME: The big question is whether FWH cycles are necessary - * for communication even if LPC_IO is defined. - */ - if (internal_buses_supported & BUS_FWH) - msg_pdbg("Registering IT85 SPI.\n"); - /* FIXME: Really leave FWH enabled? We can't use this region - * anymore since accessing it would mess up IT85 communication. - * If we decide to disable FWH for this region, we should print - * a debug message about it. - */ - /* Set this as SPI controller. */ - register_spi_master(&spi_master_it85xx); - } - return ret; +it85spi_init_error: + free(data); + return 1; } #endif -- To view, visit https://review.coreboot.org/c/flashrom/+/48196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iac1b4ae9c6f34c5265e729ae0a80024800c3c272 Gerrit-Change-Number: 48196 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

3 22

Change in flashrom[master]: it85spi.c: Factor out global state
by Anastasia Klm (Code Review) Jan. 19, 2021

Jan. 19, 2021

Anastasia Klm has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47655 ) Change subject: it85spi.c: Factor out global state ...................................................................... it85spi.c: Factor out global state Moves global state into spi_master data. BUGS=b:172876667 Change-Id: I389d34d62e753c012910aa5ff24a496b24a4753c Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M it85spi.c 1 file changed, 71 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/55/47655/1 diff --git a/it85spi.c b/it85spi.c index b998790..d6f39a4 100644 --- a/it85spi.c +++ b/it85spi.c @@ -73,11 +73,26 @@ #define INDIRECT_WRITE(base, value) OUTB(value, (base) + 4) #endif /* LPC_IO */ -#ifdef LPC_IO -static unsigned int shm_io_base; -#endif -static unsigned char *ce_high, *ce_low; -static int it85xx_scratch_rom_reenter = 0; +struct it85_data { + unsigned int shm_io_base; + unsigned char *ce_high, *ce_low; + int it85xx_scratch_rom_reenter; +}; + +static int it85xx_spi_send_command(const struct flashctx *flash, + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr); + +static struct spi_master spi_master_it85xx = { + .max_data_read = 64, + .max_data_write = 64, + .command = it85xx_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, +}; /* This function will poll the keyboard status register until either * an expected value shows up, or the timeout is reached. @@ -106,12 +121,12 @@ /* IT8502 employs a scratch RAM when flash is being updated. Call the following * two functions before/after flash erase/program. */ -static void it85xx_enter_scratch_rom(void) +static void it85xx_enter_scratch_rom(struct it85_data *data) { int ret, tries; msg_pdbg("%s():%d was called ...\n", __func__, __LINE__); - if (it85xx_scratch_rom_reenter > 0) + if (data->it85xx_scratch_rom_reenter > 0) return; #if 0 @@ -156,14 +171,14 @@ if (tries < MAX_TRY) { /* EC already runs on SRAM */ - it85xx_scratch_rom_reenter++; + data->it85xx_scratch_rom_reenter++; msg_pdbg("%s():%d * SUCCESS.\n", __func__, __LINE__); } else { msg_perr("%s():%d * Max try reached.\n", __func__, __LINE__); } } -static void it85xx_exit_scratch_rom(void) +static void it85xx_exit_scratch_rom(struct it85_data *data) { #if 0 int ret; @@ -171,7 +186,7 @@ int tries; msg_pdbg("%s():%d was called ...\n", __func__, __LINE__); - if (it85xx_scratch_rom_reenter <= 0) + if (data->it85xx_scratch_rom_reenter <= 0) return; for (tries = 0; tries < MAX_TRY; ++tries) { @@ -199,7 +214,7 @@ } if (tries < MAX_TRY) { - it85xx_scratch_rom_reenter = 0; + data->it85xx_scratch_rom_reenter = 0; msg_pdbg("%s():%d * SUCCESS.\n", __func__, __LINE__); } else { msg_perr("%s():%d * Max try reached.\n", __func__, __LINE__); @@ -217,8 +232,10 @@ static int it85xx_shutdown(void *data) { + struct it85_data *drv_data = (struct it85_data *)data; + msg_pdbg("%s():%d\n", __func__, __LINE__); - it85xx_exit_scratch_rom(); + it85xx_exit_scratch_rom(drv_data); return 0; /* FIXME: Should probably return something meaningful */ } @@ -227,31 +244,41 @@ { chipaddr base; + struct it85_data *data = calloc(1, sizeof(struct it85_data)); + if (!data) { + msg_perr("Out of memory!\n"); + return 1; + } + data->it85xx_scratch_rom_reenter = 0; + spi_master_it85xx.data = data; + msg_pdbg("%s():%d superio.vendor=0x%02x\n", __func__, __LINE__, s.vendor); - if (register_shutdown(it85xx_shutdown, NULL)) + if (register_shutdown(it85xx_shutdown, data)) { + free(data); return 1; + } #ifdef LPC_IO /* Get LPCPNP of SHM. That's big-endian. */ sio_write(s.port, LDNSEL, 0x0F); /* Set LDN to SHM (0x0F) */ - shm_io_base = (sio_read(s.port, SHM_IO_BAR0) << 8) + + data->shm_io_base = (sio_read(s.port, SHM_IO_BAR0) << 8) + sio_read(s.port, SHM_IO_BAR1); - msg_pdbg("%s():%d shm_io_base=0x%04x\n", __func__, __LINE__, - shm_io_base); + msg_pdbg("%s():%d it85_data->shm_io_base=0x%04x\n", __func__, __LINE__, + data->shm_io_base); /* These pointers are not used directly. They will be send to EC's * register for indirect access. */ base = 0xFFFFF000; - ce_high = ((unsigned char *)base) + 0xE00; /* 0xFFFFFE00 */ - ce_low = ((unsigned char *)base) + 0xD00; /* 0xFFFFFD00 */ + data->ce_high = ((unsigned char *)base) + 0xE00; /* 0xFFFFFE00 */ + data->ce_low = ((unsigned char *)base) + 0xD00; /* 0xFFFFFD00 */ /* pre-set indirect-access registers since in most of cases they are * 0xFFFFxx00. */ - INDIRECT_A0(shm_io_base, base & 0xFF); - INDIRECT_A2(shm_io_base, (base >> 16) & 0xFF); - INDIRECT_A3(shm_io_base, (base >> 24)); + INDIRECT_A0(data->shm_io_base, base & 0xFF); + INDIRECT_A2(data->shm_io_base, (base >> 16) & 0xFF); + INDIRECT_A3(data->shm_io_base, (base >> 24)); #endif #ifdef LPC_MEMORY /* FIXME: We should block accessing that region for anything else. @@ -263,28 +290,13 @@ msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__, (unsigned int)base); - ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */ - ce_low = (unsigned char *)(base + 0xD00); /* 0xFFFFFD00 */ + data->ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */ + data->ce_low = (unsigned char *)(base + 0xD00); /* 0xFFFFFD00 */ #endif return 0; } -static int it85xx_spi_send_command(const struct flashctx *flash, - unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, - unsigned char *readarr); - -static const struct spi_master spi_master_it85xx = { - .max_data_read = 64, - .max_data_write = 64, - .command = it85xx_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, -}; - int it85xx_spi_init(struct superio s) { int ret; @@ -328,42 +340,51 @@ unsigned char *readarr) { unsigned int i; + if (!(flash->mst)) { + msg_perr("No data in flash context!\n"); + return 1; + } + struct it85_data *data = (struct it85_data *) flash->mst->spi.data; + if (!data) { + msg_perr("No data in flash context!\n"); + return 1; + } - it85xx_enter_scratch_rom(); + it85xx_enter_scratch_rom(data); /* Exit scratch ROM ONLY when programmer shuts down. Otherwise, the * temporary flash state may halt the EC. */ #ifdef LPC_IO - INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); - INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/ - INDIRECT_A1(shm_io_base, (((unsigned long int)ce_low) >> 8) & 0xff); + INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_high) >> 8) & 0xff); + INDIRECT_WRITE(data->shm_io_base, 0xFF); /* Write anything to this address.*/ + INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_low) >> 8) & 0xff); #endif #ifdef LPC_MEMORY - mmio_writeb(0, ce_high); + mmio_writeb(0, data->ce_high); #endif for (i = 0; i < writecnt; ++i) { #ifdef LPC_IO - INDIRECT_WRITE(shm_io_base, writearr[i]); + INDIRECT_WRITE(data->shm_io_base, writearr[i]); #endif #ifdef LPC_MEMORY - mmio_writeb(writearr[i], ce_low); + mmio_writeb(writearr[i], data->ce_low); #endif } for (i = 0; i < readcnt; ++i) { #ifdef LPC_IO - readarr[i] = INDIRECT_READ(shm_io_base); + readarr[i] = INDIRECT_READ(data->shm_io_base); #endif #ifdef LPC_MEMORY - readarr[i] = mmio_readb(ce_low); + readarr[i] = mmio_readb(data->ce_low); #endif } #ifdef LPC_IO - INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); - INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/ + INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_high) >> 8) & 0xff); + INDIRECT_WRITE(data->shm_io_base, 0xFF); /* Write anything to this address.*/ #endif #ifdef LPC_MEMORY - mmio_writeb(0, ce_high); + mmio_writeb(0, data->ce_high); #endif return 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/47655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I389d34d62e753c012910aa5ff24a496b24a4753c Gerrit-Change-Number: 47655 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klm <aklm(a)chromium.org> Gerrit-MessageType: newchange

6 55

Change in flashrom[master]: WIP: spi25_statusreg.c: restore SR contents at flashrom exit
by Nikolai Artemiev (Code Review) Jan. 13, 2021

Jan. 13, 2021

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48778 ) Change subject: WIP: spi25_statusreg.c: restore SR contents at flashrom exit ...................................................................... WIP: spi25_statusreg.c: restore SR contents at flashrom exit spi_disable_blockprotect_generic() now uses register_chip_restore() to reset the chip's status register at flashrom exit. Imported from cros flashrom at `b170dd4e1d5c33b169c5` Change-Id: If2f0e73518d40519b7569f627c90a34c364df47c Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M spi25_statusreg.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/48778/1 diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 34f9ad4..5dda912 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -108,6 +108,12 @@ return readarr[0]; } +static int spi_restore_status(struct flashctx *flash, uint8_t status) +{ + msg_cdbg("restoring chip status (0x%02x)\n", status); + return spi_write_status_register(flash, status); +} + /* A generic block protection disable. * Tests if a protection is enabled with the block protection mask (bp_mask) and returns success otherwise. * Tests if the register bits are locked with the lock_mask (lock_mask). @@ -139,6 +145,9 @@ return 0; } + /* restore status register content upon exit */ + register_chip_restore(spi_restore_status, flash, status); + msg_cdbg("Some block protection in effect, disabling... "); if ((status & lock_mask) != 0) { msg_cdbg("\n\tNeed to disable the register lock first... "); -- To view, visit https://review.coreboot.org/c/flashrom/+/48778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If2f0e73518d40519b7569f627c90a34c364df47c Gerrit-Change-Number: 48778 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

2 9

Change in flashrom[master]: Makefile: Add a DISABLE_CLOCK_GETTIME option
by Martin Lucina (Code Review) Jan. 11, 2021

Jan. 11, 2021

Martin Lucina has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48796 ) Change subject: Makefile: Add a DISABLE_CLOCK_GETTIME option ...................................................................... Makefile: Add a DISABLE_CLOCK_GETTIME option Allows to force-disable the use of clock_gettime() at build time, falling back to busy-looping for udelay. This is useful when building for systems which are known to lie about the resolution of clock_gettime(). Change-Id: I645a5d3f29ffdbd24a58127ab73d7d8755304f45 Signed-off-by: Martin Lucina <martin(a)lucina.net> --- M Makefile 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/48796/1 diff --git a/Makefile b/Makefile index 1f7ea46..09b2154 100644 --- a/Makefile +++ b/Makefile @@ -1663,12 +1663,17 @@ ( echo "found."; echo "UTSNAME := yes" >> .features.tmp ) || \ ( echo "not found."; echo "UTSNAME := no" >> .features.tmp ) } 2>>$(BUILD_DETAILS_FILE) | tee -a $(BUILD_DETAILS_FILE) @printf "Checking for clock_gettime support... " | tee -a $(BUILD_DETAILS_FILE) +ifeq ($(DISABLE_CLOCK_GETTIME), yes) + @ { ( echo "disabled."; echo "CLOCK_GETTIME := no" >>.features.tmp ) } \ + 2>>$(BUILD_DETAILS_FILE) | tee -a $(BUILD_DETAILS_FILE) +else @echo "$$CLOCK_GETTIME_TEST" >.featuretest.c @printf "\nexec: %s\n" "$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -lrt .featuretest.c -o .featuretest$(EXEC_SUFFIX)" >>$(BUILD_DETAILS_FILE) @ { $(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -lrt .featuretest.c -o .featuretest$(EXEC_SUFFIX) >&2 && \ ( echo "found."; echo "CLOCK_GETTIME := yes" >>.features.tmp ) || \ ( echo "not found."; echo "CLOCK_GETTIME := no" >>.features.tmp ) } \ 2>>$(BUILD_DETAILS_FILE) | tee -a $(BUILD_DETAILS_FILE) +endif @$(DIFF) -q .features.tmp .features >/dev/null 2>&1 && rm .features.tmp || mv .features.tmp .features @rm -f .featuretest.c .featuretest$(EXEC_SUFFIX) -- To view, visit https://review.coreboot.org/c/flashrom/+/48796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I645a5d3f29ffdbd24a58127ab73d7d8755304f45 Gerrit-Change-Number: 48796 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Lucina <martin(a)lucina.net> Gerrit-MessageType: newchange

2 6

Change in flashrom[master]: realtek_mst_i2c_spi.c: Make consistent with std=c99
by Edward O'Callaghan (Code Review) Jan. 10, 2021

Jan. 10, 2021

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47909 ) Change subject: realtek_mst_i2c_spi.c: Make consistent with std=c99 ...................................................................... realtek_mst_i2c_spi.c: Make consistent with std=c99 Use 'modern' C to scope iterator declarations only to the loop constructs they are used in. BUG=none TEST=builds Change-Id: I9d9d1bf01209a7840f7b3fa2c6f7592375a74330 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M realtek_mst_i2c_spi.c 1 file changed, 4 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/09/47909/1 diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 538b07a..151f7f6 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -205,7 +205,6 @@ const unsigned char *writearr, unsigned char *readarr) { - unsigned i; int max_timeout_mul = 1; int ret = 0; @@ -262,7 +261,7 @@ ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, ctrl_reg_val); ret |= realtek_mst_i2c_spi_write_register(fd, 0x61, writearr[0]); /* opcode */ - for (i = 0; i < writecnt; ++i) + for (unsigned i = 0; i < writecnt; ++i) ret |= realtek_mst_i2c_spi_write_register(fd, 0x64 + i, writearr[i + 1]); ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, ctrl_reg_val | 0x1); if (ret) @@ -272,7 +271,7 @@ if (ret) return ret; - for (i = 0; i < readcnt; ++i) + for (unsigned i = 0; i < readcnt; ++i) ret |= realtek_mst_i2c_spi_read_register(fd, 0x67 + i, &readarr[i]); return ret; @@ -306,7 +305,6 @@ static int realtek_mst_i2c_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) { - unsigned i; int ret = 0; if (start & 0xff) @@ -339,7 +337,7 @@ uint8_t dummy; realtek_mst_i2c_spi_read_register(fd, MCU_DATA_PORT, &dummy); - for (i = 0; i < len; i += PAGE_SIZE) { + for (unsigned i = 0; i < len; i += PAGE_SIZE) { ret |= realtek_mst_i2c_spi_read_data(fd, REGISTER_ADDRESS, buf + i, min(len - i, PAGE_SIZE)); if (ret) @@ -352,7 +350,6 @@ static int realtek_mst_i2c_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len) { - unsigned i; int ret = 0; if (start & 0xff) @@ -369,7 +366,7 @@ ret |= realtek_mst_i2c_spi_write_register(fd, 0x6D, 0x02); /* write opcode */ ret |= realtek_mst_i2c_spi_write_register(fd, 0x71, (PAGE_SIZE - 1)); /* fit len=256 */ - for (i = 0; i < len; i += PAGE_SIZE) { + for (unsigned i = 0; i < len; i += PAGE_SIZE) { uint16_t page_len = min(len - i, PAGE_SIZE); if (len - i < PAGE_SIZE) ret |= realtek_mst_i2c_spi_write_register(fd, 0x71, page_len-1); -- To view, visit https://review.coreboot.org/c/flashrom/+/47909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9d9d1bf01209a7840f7b3fa2c6f7592375a74330 Gerrit-Change-Number: 47909 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 2

Change in flashrom[master]: lspcon_i2c_spi.c: Make consistent with std=c99
by Edward O'Callaghan (Code Review) Jan. 10, 2021

Jan. 10, 2021

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47910 ) Change subject: lspcon_i2c_spi.c: Make consistent with std=c99 ...................................................................... lspcon_i2c_spi.c: Make consistent with std=c99 Use 'modern' C to scope iterator declarations only to the loop constructs they are used in. BUG=none TEST=builds Change-Id: Id61f8416416d2f625d424760e00f94dc730105f4 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M lspcon_i2c_spi.c 1 file changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/10/47910/1 diff --git a/lspcon_i2c_spi.c b/lspcon_i2c_spi.c index 7b9f1c0..6ee2840 100644 --- a/lspcon_i2c_spi.c +++ b/lspcon_i2c_spi.c @@ -127,14 +127,13 @@ static int lspcon_i2c_spi_register_control(int fd, packet_t *packet) { - int i; int ret = lspcon_i2c_spi_write_register(fd, SWSPI_WDATA, packet->command); if (ret) return ret; /* Higher 4 bits are read size. */ int write_size = packet->data_size & 0x0f; - for (i = 0; i < write_size; ++i) { + for (unsigned i = 0; i < write_size; ++i) { ret |= lspcon_i2c_spi_write_register(fd, SWSPI_WDATA, packet->data[i]); } @@ -256,7 +255,6 @@ const unsigned char *writearr, unsigned char *readarr) { - unsigned int i; if (writecnt > 16 || readcnt > 16 || writecnt == 0) { msg_perr("%s: Invalid read/write count for send command.\n", __func__); @@ -285,7 +283,7 @@ if (ret) return ret; - for (i = 0; i < readcnt; ++i) { + for (unsigned i = 0; i < readcnt; ++i) { ret |= lspcon_i2c_spi_read_register(fd, SWSPI_RDATA, &readarr[i]); } @@ -340,7 +338,6 @@ static int lspcon_i2c_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) { - unsigned int i; int ret = 0; if (start & 0xff) return default_spi_read(flash, buf, start, len); @@ -349,7 +346,7 @@ if (fd < 0) return SPI_GENERIC_ERROR; - for (i = 0; i < len; i += PAGE_SIZE) { + for (unsigned i = 0; i < len; i += PAGE_SIZE) { ret |= lspcon_i2c_spi_map_page(fd, start + i); ret |= lspcon_i2c_spi_read_data(fd, PAGE_ADDRESS, buf + i, min(len - i, PAGE_SIZE)); } -- To view, visit https://review.coreboot.org/c/flashrom/+/47910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id61f8416416d2f625d424760e00f94dc730105f4 Gerrit-Change-Number: 47910 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips: upstream AT25SF128A from chromiumos
by Alan Green (Code Review) Jan. 6, 2021

Jan. 6, 2021

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/37543 ) Change subject: flashchips: upstream AT25SF128A from chromiumos ...................................................................... flashchips: upstream AT25SF128A from chromiumos Upstream the AT25SF128A chip from chromiumos repository. Change-Id: I6349aa41eee0c997aaa507383aff7ce26441d24f --- M flashchips.c M flashchips.h 2 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/43/37543/1 diff --git a/flashchips.c b/flashchips.c index 4324c11..fc4cdff 100644 --- a/flashchips.c +++ b/flashchips.c @@ -2293,6 +2293,44 @@ { .vendor = "Atmel", + .name = "AT25SF128A", + .bustype = BUS_SPI, + .manufacture_id = ATMEL_ID, + .model_id = ATMEL_AT25SF128A, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PR, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp4_srwd, + .unlock = spi_disable_blockprotect_bp4_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Atmel", .name = "AT25SF161", .bustype = BUS_SPI, .manufacture_id = ATMEL_ID, diff --git a/flashchips.h b/flashchips.h index 2c2da6c..5609527 100644 --- a/flashchips.h +++ b/flashchips.h @@ -151,6 +151,7 @@ #define ATMEL_AT25SF081 0x8501 #define ATMEL_AT25SF161 0x8601 #define ATMEL_AT25SL128A 0x4218 +#define ATMEL_AT25SF128A 0x8901 /* Adesto AT25SF128A */ #define ATMEL_AT26DF041 0x4400 #define ATMEL_AT26DF081 0x4500 /* guessed, no datasheet available */ #define ATMEL_AT26DF081A 0x4501 -- To view, visit https://review.coreboot.org/c/flashrom/+/37543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6349aa41eee0c997aaa507383aff7ce26441d24f Gerrit-Change-Number: 37543 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips.c: Take GD25LQ128C/D from downstream
by Alan Green (Code Review) Jan. 6, 2021

Jan. 6, 2021

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/35478 ) Change subject: flashchips.c: Take GD25LQ128C/D from downstream ...................................................................... flashchips.c: Take GD25LQ128C/D from downstream Take the diffs for GD25LQ128C/D from the ChromiumOS flashrom repo. This chips was added in Chromium OS `commit 62cd8106` by furquan(a)google.com on 2016-07-18, and has been marked tested. Signed-off-by: Alan Green <avg(a)google.com> Change-Id: I4358392520507ddbfc654feb49fa982d49db2f28 --- M flashchips.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/35478/1 diff --git a/flashchips.c b/flashchips.c index 3994c93..5c797fd 100644 --- a/flashchips.c +++ b/flashchips.c @@ -5894,7 +5894,7 @@ .page_size = 256, /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -5916,8 +5916,7 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_bp4_srwd, - .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1695, 1950}, -- To view, visit https://review.coreboot.org/c/flashrom/+/35478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I4358392520507ddbfc654feb49fa982d49db2f28 Gerrit-Change-Number: 35478 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips.c: Take GD25LQ40 from downstream
by Alan Green (Code Review) Jan. 6, 2021

Jan. 6, 2021

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/35479 ) Change subject: flashchips.c: Take GD25LQ40 from downstream ...................................................................... flashchips.c: Take GD25LQ40 from downstream Take definition of GD25LQ40 from ChromiumOS repository. This chip was added in `commit 59543cd1` by dnschneid(a)chromium.org on 2016-04-27. The commit message notes that some testing had been done, even thought the .tested attribute was left as UNTESTED. Signed-off-by: Alan Green <avg(a)google.com> Change-Id: I978745b38536cda807adf07af4e4d093d0d93ad1 --- M flashchips.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/35479/1 diff --git a/flashchips.c b/flashchips.c index 5c797fd..ac07fa8 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6009,7 +6009,7 @@ .total_size = 512, .page_size = 256, /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -6032,8 +6032,7 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_bp4_srwd, - .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1695, 1950}, -- To view, visit https://review.coreboot.org/c/flashrom/+/35479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I978745b38536cda807adf07af4e4d093d0d93ad1 Gerrit-Change-Number: 35479 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: realtek_mst_i2c_spi.c: Consolidate shifts to the one fn
by Edward O'Callaghan (Code Review) Jan. 2, 2021

Jan. 2, 2021

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48975 ) Change subject: realtek_mst_i2c_spi.c: Consolidate shifts to the one fn ...................................................................... realtek_mst_i2c_spi.c: Consolidate shifts to the one fn To avoid further incorrect mappings ensure all the shifting happens within realtek_mst_i2c_spi_map_page() itself. BUG=none BRANCH=none TEST=builds Change-Id: I96c595b1abae044347fb0c2c91b891a60dd3675e Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Suggested-by: Angel Pons <th3fanbus(a)gmail.com> --- M realtek_mst_i2c_spi.c 1 file changed, 8 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/75/48975/1 diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 3e84b23..418e23a 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -289,9 +289,14 @@ return ret; } -static int realtek_mst_i2c_spi_map_page(int fd, uint8_t block_idx, uint8_t page_idx, uint8_t byte_idx) +static int realtek_mst_i2c_spi_map_page(int fd, uint32_t addr) { int ret = 0; + + uint8_t block_idx = (addr >> 16) & 0xff; + uint8_t page_idx = (addr >> 8) & 0xff; + uint8_t byte_idx = addr & 0xff; + ret |= realtek_mst_i2c_spi_write_register(fd, MAP_PAGE_BYTE2, block_idx); ret |= realtek_mst_i2c_spi_write_register(fd, MAP_PAGE_BYTE1, page_idx); ret |= realtek_mst_i2c_spi_write_register(fd, MAP_PAGE_BYTE0, byte_idx); @@ -330,10 +335,7 @@ start--; ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, 0x46); // ** ret |= realtek_mst_i2c_spi_write_register(fd, 0x61, OPCODE_READ); - uint8_t block_idx = (start >> 16) & 0xff; - uint8_t page_idx = (start >> 8) & 0xff; - uint8_t byte_idx = start & 0xff; - ret |= realtek_mst_i2c_spi_map_page(fd, block_idx, page_idx, byte_idx); + ret |= realtek_mst_i2c_spi_map_page(fd, start); ret |= realtek_mst_i2c_spi_write_register(fd, 0x6a, 0x03); ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, 0x47); // ** if (ret) @@ -384,10 +386,7 @@ uint16_t page_len = min(len - i, PAGE_SIZE); if (len - i < PAGE_SIZE) ret |= realtek_mst_i2c_spi_write_register(fd, 0x71, page_len-1); - uint8_t block_idx = ((start + i) >> 16) & 0xff; - uint8_t page_idx = ((start + i) >> 8) & 0xff; - uint8_t byte_idx = (start + i) & 0xff; - ret |= realtek_mst_i2c_spi_map_page(fd, block_idx, page_idx, byte_idx); + ret |= realtek_mst_i2c_spi_map_page(fd, (start + i)); if (ret) break; -- To view, visit https://review.coreboot.org/c/flashrom/+/48975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I96c595b1abae044347fb0c2c91b891a60dd3675e Gerrit-Change-Number: 48975 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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