December 2020 - flashrom-gerrit

Change in flashrom[master]: chipset_enable.c: change "Broadwell U Base" NT->OK
by Nikolai Artemiev (Code Review) 14 Dec '20

14 Dec '20

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47218 ) Change subject: chipset_enable.c: change "Broadwell U Base" NT->OK ...................................................................... chipset_enable.c: change "Broadwell U Base" NT->OK Change-Id: I0b4d1dd2b271537faea15856442fe183d9de3318 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/47218/1 diff --git a/chipset_enable.c b/chipset_enable.c index 4273478..77d07a1 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1997,7 +1997,7 @@ {0x8086, 0x9cc1, B_FS, NT, "Intel", "Haswell U Sample", enable_flash_pch9_lp}, {0x8086, 0x9cc2, B_FS, NT, "Intel", "Broadwell U Sample", enable_flash_pch9_lp}, {0x8086, 0x9cc3, B_FS, DEP, "Intel", "Broadwell U Premium", enable_flash_pch9_lp}, - {0x8086, 0x9cc5, B_FS, NT, "Intel", "Broadwell U Base", enable_flash_pch9_lp}, + {0x8086, 0x9cc5, B_FS, OK, "Intel", "Broadwell U Base", enable_flash_pch9_lp}, {0x8086, 0x9cc6, B_FS, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9_lp}, {0x8086, 0x9cc7, B_FS, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp}, {0x8086, 0x9cc9, B_FS, NT, "Intel", "Broadwell Y Base", enable_flash_pch9_lp}, -- To view, visit https://review.coreboot.org/c/flashrom/+/47218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I0b4d1dd2b271537faea15856442fe183d9de3318 Gerrit-Change-Number: 47218 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips.c: Add Sanyo LF25FW203A entry
by Nikolai Artemiev (Code Review) 13 Dec '20

13 Dec '20

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48443 ) Change subject: flashchips.c: Add Sanyo LF25FW203A entry ...................................................................... flashchips.c: Add Sanyo LF25FW203A entry Chip imported from cros flashrom at `commit e50562c68fc4901acb6243b4f4d2c182a162ad41` Change-Id: I530e123e49d50b032496f18efce438e9ad7e7552 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M flashchips.c 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/43/48443/1 diff --git a/flashchips.c b/flashchips.c index bc5de4a..76b530a 100644 --- a/flashchips.c +++ b/flashchips.c @@ -15659,6 +15659,32 @@ }, { + .vendor = "Sanyo", + .name = "LF25FW203A", + .bustype = BUS_SPI, + .manufacture_id = SANYO_ID, + .model_id = SANYO_LE25FW203A, + .total_size = 2048, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { .vendor = "Sharp", .name = "LH28F008BJT-BTLZ1", .bustype = BUS_PARALLEL, -- To view, visit https://review.coreboot.org/c/flashrom/+/48443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I530e123e49d50b032496f18efce438e9ad7e7552 Gerrit-Change-Number: 48443 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: meson: Add missing config option for J-Link SPI
by zapb (Code Review) 13 Dec '20

13 Dec '20

zapb has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48478 ) Change subject: meson: Add missing config option for J-Link SPI ...................................................................... meson: Add missing config option for J-Link SPI Signed-off-by: Marc Schink <dev(a)zapb.de> Change-Id: I476c649f9db7342688560aac9ee5df056517a028 --- M meson.build M meson_options.txt 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/48478/1 diff --git a/meson.build b/meson.build index fd5a5ef..556183e 100644 --- a/meson.build +++ b/meson.build @@ -38,6 +38,7 @@ config_dediprog = get_option('config_dediprog') config_developerbox_spi = get_option('config_developerbox_spi') config_digilent_spi = get_option('config_digilent_spi') +config_jlink_spi = get_option('config_jlink_spi') config_drkaiser = get_option('config_drkaiser') config_dummy = get_option('config_dummy') config_ene_lpc = get_option('config_ene_lpc') @@ -159,6 +160,11 @@ srcs += 'digilent_spi.c' cargs += '-DCONFIG_DIGILENT_SPI=1' endif +if config_jlink_spi + srcs += 'jlink_spi.c' + cargs += '-DCONFIG_JLINK_SPI=1' + deps += dependency('libjaylink') +endif if config_drkaiser srcs += 'drkaiser.c' cargs += '-DCONFIG_DRKAISER=1' diff --git a/meson_options.txt b/meson_options.txt index 9c0a798..89fcbee 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -9,6 +9,7 @@ option('config_dediprog', type : 'boolean', value : true, description : 'Dediprog SF100') option('config_developerbox_spi', type : 'boolean', value : true, description : 'Developerbox emergency recovery') option('config_digilent_spi', type : 'boolean', value : true, description : 'Digilent Development board JTAG') +option('config_jlink_spi', type : 'boolean', value : false, description : 'SEGGER J-Link and compatible devices') option('config_drkaiser', type : 'boolean', value : true, description : 'Dr. Kaiser') option('config_dummy', type : 'boolean', value : true, description : 'dummy tracing') option('config_ene_lpc', type : 'boolean', value : true, description : 'ENE LPC interface keyboard controller') -- To view, visit https://review.coreboot.org/c/flashrom/+/48478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I476c649f9db7342688560aac9ee5df056517a028 Gerrit-Change-Number: 48478 Gerrit-PatchSet: 1 Gerrit-Owner: zapb <dev(a)zapb.de> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips: Mark Intel 25F640S33B8 as TESTED_PREW
by Miklós Márton (Code Review) 11 Dec '20

11 Dec '20

Miklós Márton has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44342 ) Change subject: flashchips: Mark Intel 25F640S33B8 as TESTED_PREW ...................................................................... flashchips: Mark Intel 25F640S33B8 as TESTED_PREW Tested with ch341a_spi from an Atheros AP81 reference board. Change-Id: I67b5962a1ae26fd1bc7e3889f1616def28b599ef Signed-off-by: Zoltan HERPAI <wigyori(a)uid0.hu> --- M flashchips.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/42/44342/1 diff --git a/flashchips.c b/flashchips.c index 09ac9b4..1506410 100644 --- a/flashchips.c +++ b/flashchips.c @@ -7503,7 +7503,7 @@ .page_size = 256, /* OTP: 506B total (2x 8B, 30x 16B, 1x 10B); read 0x4B; write 0x42 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = -- To view, visit https://review.coreboot.org/c/flashrom/+/44342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I67b5962a1ae26fd1bc7e3889f1616def28b599ef Gerrit-Change-Number: 44342 Gerrit-PatchSet: 1 Gerrit-Owner: Miklós Márton <martonmiklosqdev(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: cli_classic.c: fix minor cosmetic bug when support for wiki page gene...
by Idwer Vollering (Code Review) 08 Dec '20

08 Dec '20

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48430 ) Change subject: cli_classic.c: fix minor cosmetic bug when support for wiki page generation is not compiled in ...................................................................... cli_classic.c: fix minor cosmetic bug when support for wiki page generation is not compiled in Change-Id: I222fd7aa5d633fe81ef1894d67dcb25ba0dd8937 --- M cli_classic.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/30/48430/1 diff --git a/cli_classic.c b/cli_classic.c index ae7f6ef..3dbaec2 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -364,7 +364,7 @@ cli_classic_validate_singleop(&operation_specified); list_supported_wiki = 1; #else - cli_classic_abort_usage("Error: Wiki output was not" + cli_classic_abort_usage("Error: Wiki output was not " "compiled in. Aborting.\n"); #endif break; -- To view, visit https://review.coreboot.org/c/flashrom/+/48430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I222fd7aa5d633fe81ef1894d67dcb25ba0dd8937 Gerrit-Change-Number: 48430 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: WIP: flashchips.c: import chips from cros flashrom
by Nikolai Artemiev (Code Review) 03 Dec '20

03 Dec '20

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46064 ) Change subject: WIP: flashchips.c: import chips from cros flashrom ...................................................................... WIP: flashchips.c: import chips from cros flashrom Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> Change-Id: If6b23ad2e65258143e0045133828d9db119fb665 --- M flashchips.c 1 file changed, 217 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/46064/1 diff --git a/flashchips.c b/flashchips.c index 7d10abf..82dbf70 100644 --- a/flashchips.c +++ b/flashchips.c @@ -15814,6 +15814,68 @@ { .vendor = "Spansion", + .name = "S25FL128S_UL Uniform 128 kB Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL128S_UL, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {128 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", + .name = "S25FL128S_US Uniform 64 kB Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL128S_US, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", .name = "S25FL129P......0", /* hybrid: 32 (top or bottom) 4 kB sub-sectors + 64 kB sectors */ .bustype = BUS_SPI, .manufacture_id = SPANSION_ID, @@ -16038,6 +16100,62 @@ { .vendor = "Spansion", + .name = "S25FL256S Large Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL256S_UL, + .total_size = 16384, /* This is just half the size.... */ + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {256 * 1024, 64} }, + .block_erase = s25fl_block_erase, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", + .name = "S25FL256S Small Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL256S_US, + .total_size = 16384, /* This is just half the size.... */ + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = s25fl_block_erase, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", .name = "S25FL256S......0", /* hybrid: 32 (top or bottom) 4 kB sub-sectors + 64 kB sectors */ .bustype = BUS_SPI, .manufacture_id = SPANSION_ID, @@ -16116,6 +16234,68 @@ }, { + .vendor = "Spansion", + .name = "S25FS128S Large Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FS128S_L, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = s25fs_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", + .name = "S25FS128S Small Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FS128S_S, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = s25fs_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { .vendor = "SyncMOS/MoselVitelic", .name = "{F,S,V}29C51001B", .bustype = BUS_PARALLEL, @@ -17014,6 +17194,43 @@ { .vendor = "Winbond", + .name = "W25Q32JW", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q32JW, + .total_size = 4096, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 1950}, + }, + + { + .vendor = "Winbond", .name = "W25Q40.V", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, -- To view, visit https://review.coreboot.org/c/flashrom/+/46064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If6b23ad2e65258143e0045133828d9db119fb665 Gerrit-Change-Number: 46064 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: WIP: s25f.c: import file from cros flashrom
by Nikolai Artemiev (Code Review) 03 Dec '20

03 Dec '20

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46140 ) Change subject: WIP: s25f.c: import file from cros flashrom ...................................................................... WIP: s25f.c: import file from cros flashrom Imported from cros flashrom at hash `9c4c9a56b6a0370b383df9c75d71b3bd469e672d` Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> Change-Id: I2d23f9c36ce8b2959807fbeee7f60e02444e3763 --- M Makefile M chipdrivers.h M flash.h M flashrom.c A s25f.c M spi.h 6 files changed, 585 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/40/46140/1 diff --git a/Makefile b/Makefile index 8af7042..2de7131 100644 --- a/Makefile +++ b/Makefile @@ -638,7 +638,7 @@ CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \ sst28sf040.o 82802ab.o \ sst49lfxxxc.o sst_fwhub.o edi.o flashchips.o spi.o spi25.o spi25_statusreg.o \ - spi95.o opaque.o sfdp.o en29lv640b.o at45db.o writeprotect.o + spi95.o opaque.o sfdp.o en29lv640b.o at45db.o writeprotect.o s25f.o ############################################################################### # Library code. diff --git a/chipdrivers.h b/chipdrivers.h index cf03811..225dce7 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -20,7 +20,8 @@ #ifndef __CHIPDRIVERS_H__ #define __CHIPDRIVERS_H__ 1 -#include "flash.h" /* for chipaddr and flashctx */ +#include "flash.h" /* for chipaddr and flashctx */ +#include "writeprotect.h" /* for modifier_bits */ /* spi.c */ int spi_aai_write(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); @@ -170,6 +171,15 @@ int printlock_sst_fwhub(struct flashctx *flash); int unlock_sst_fwhub(struct flashctx *flash); +/* s25fl.c */ +int probe_spi_big_spansion(struct flashctx *flash); +int s25fl_block_erase(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + +/* s25f.c */ +int s25f_get_modifier_bits(const struct flashctx *flash, struct modifier_bits *m); +int s25f_set_modifier_bits(const struct flashctx *flash, struct modifier_bits *m); +int s25fs_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + /* w39.c */ int printlock_w39f010(struct flashctx * flash); int printlock_w39l010(struct flashctx * flash); diff --git a/flash.h b/flash.h index fefca9d..db64966 100644 --- a/flash.h +++ b/flash.h @@ -49,11 +49,17 @@ #define ERROR_OOM -100 #define TIMEOUT_ERROR -101 +struct flashrom_flashctx; +#define flashctx flashrom_flashctx /* TODO: Agree on a name and convert all occurences. */ + /* TODO: check using code for correct usage of types */ typedef uintptr_t chipaddr; #define PRIxPTR_WIDTH ((int)(sizeof(uintptr_t)*2)) int register_shutdown(int (*function) (void *data), void *data); +#define CHIP_RESTORE_CALLBACK int (*func) (struct flashctx *flash, uint8_t status) + +int register_chip_restore(CHIP_RESTORE_CALLBACK, struct flashctx *flash, uint8_t status); int shutdown_free(void *data); void *programmer_map_flash_region(const char *descr, uintptr_t phys_addr, size_t len); void programmer_unmap_flash_region(void *virt_addr, size_t len); @@ -163,8 +169,6 @@ #define TEST_BAD_PRE (struct tested){ .probe = BAD, .read = BAD, .erase = BAD, .write = NT } #define TEST_BAD_PREW (struct tested){ .probe = BAD, .read = BAD, .erase = BAD, .write = BAD } -struct flashrom_flashctx; -#define flashctx flashrom_flashctx /* TODO: Agree on a name and convert all occurences. */ typedef int (erasefunc_t)(struct flashctx *flash, unsigned int addr, unsigned int blocklen); struct flashchip { diff --git a/flashrom.c b/flashrom.c index c18a04f..6ed863b 100644 --- a/flashrom.c +++ b/flashrom.c @@ -536,6 +536,15 @@ {0}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; +#define CHIP_RESTORE_MAXFN 4 +static int chip_restore_fn_count = 0; +static struct chip_restore_func_data { + CHIP_RESTORE_CALLBACK; + struct flashctx *flash; + uint8_t status; +} chip_restore_fn[CHIP_RESTORE_MAXFN]; + + #define SHUTDOWN_MAXFN 32 static int shutdown_fn_count = 0; /** @private */ @@ -586,6 +595,23 @@ return 0; } +//int register_chip_restore(int (*function) (void *data), void *data) +int register_chip_restore(CHIP_RESTORE_CALLBACK, + struct flashctx *flash, uint8_t status) +{ + if (chip_restore_fn_count >= CHIP_RESTORE_MAXFN) { + msg_perr("Tried to register more than %i chip restore" + " functions.\n", CHIP_RESTORE_MAXFN); + return 1; + } + chip_restore_fn[chip_restore_fn_count].func = func; /* from macro */ + chip_restore_fn[chip_restore_fn_count].flash = flash; + chip_restore_fn[chip_restore_fn_count].status = status; + chip_restore_fn_count++; + + return 0; +} + int programmer_init(enum programmer prog, const char *param) { int ret; diff --git a/s25f.c b/s25f.c new file mode 100644 index 0000000..a30618c --- /dev/null +++ b/s25f.c @@ -0,0 +1,535 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2014 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * Neither the name of Google or the names of contributors or + * licensors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * This software is provided "AS IS," without a warranty of any kind. + * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, + * INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. + * GOOGLE INC AND ITS LICENSORS SHALL NOT BE LIABLE + * FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING + * OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL + * GOOGLE OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, + * OR FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR + * PUNITIVE DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF + * LIABILITY, ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, + * EVEN IF GOOGLE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * + * s25f.c - Helper functions for Spansion S25FL and S25FS SPI flash chips. + * Uses 24 bit addressing for the FS chips and 32 bit addressing for the FL + * chips (which is required by the overlayed sector size devices). + * TODO: Implement fancy hybrid sector architecture helpers. + */ + +#include <string.h> + +#include "chipdrivers.h" +#include "hwaccess.h" +#include "spi.h" +#include "writeprotect.h" + +/* + * RDAR and WRAR are supported on chips which have more than one set of status + * and control registers and take an address of the register to read/write. + * WRR, RDSR2, and RDCR are used on chips with a more limited set of control/ + * status registers. + * + * WRR is somewhat peculiar. It shares the same opcode as JEDEC_WRSR, and if + * given one data byte (following the opcode) it acts the same way. If it's + * given two data bytes, the first data byte overwrites status register 1 + * and the second data byte overwrites config register 1. + */ +#define CMD_WRR 0x01 +#define CMD_WRDI 0x04 +#define CMD_RDSR2 0x07 /* note: read SR1 with JEDEC RDSR opcode */ +#define CMD_RDCR 0x35 +#define CMD_RDAR 0x65 +#define CMD_WRAR 0x71 + +/* TODO: For now, commands which use an address assume 24-bit addressing */ +#define CMD_WRR_LEN 3 +#define CMD_WRDI_LEN 1 +#define CMD_RDAR_LEN 4 +#define CMD_WRAR_LEN 5 + +#define CMD_RSTEN 0x66 +#define CMD_RST 0x99 + +#define CR1NV_ADDR 0x000002 +#define CR1_BPNV_O (1 << 3) +#define CR1_TBPROT_O (1 << 5) +#define CR3NV_ADDR 0x000004 +#define CR3NV_20H_NV (1 << 3) + +/* See "Embedded Algorithm Performance Tables for additional timing specs. */ +#define T_W 145 * 1000 /* NV register write time (145ms) */ +#define T_RPH 35 /* Reset pulse hold time (35us) */ +#define S25FS_T_SE 145 * 1000 /* Sector Erase Time (145ms) */ +#define S25FL_T_SE 130 * 1000 /* Sector Erase Time (130ms) */ + +static int s25f_legacy_software_reset(const struct flashctx *flash) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = 1, + .writearr = (const unsigned char[]){ CMD_RSTEN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 1, + .writearr = (const unsigned char[]){ 0xf0 }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution\n", __func__); + return result; + } + + /* Allow time for reset command to execute. The datasheet specifies + * Trph = 35us, double that to be safe. */ + programmer_delay(T_RPH * 2); + + return 0; +} + +/* "Legacy software reset" is disabled by default on S25FS, use this instead. */ +static int s25fs_software_reset(struct flashctx *flash) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = 1, + .writearr = (const unsigned char[]){ CMD_RSTEN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 1, + .writearr = (const unsigned char[]){ CMD_RST }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution\n", __func__); + return result; + } + + /* Allow time for reset command to execute. Double tRPH to be safe. */ + programmer_delay(T_RPH * 2); + + return 0; +} + +static int s25f_poll_status(const struct flashctx *flash) +{ + uint8_t tmp = spi_read_status_register(flash); + + while (tmp & SPI_SR_WIP) { + /* + * The WIP bit on S25F chips remains set to 1 if erase or + * programming errors occur, so we must check for those + * errors here. If an error is encountered, do a software + * reset to clear WIP and other volatile bits, otherwise + * the chip will be unresponsive to further commands. + */ + if (tmp & SPI_SR_ERA_ERR) { + msg_cerr("Erase error occurred\n"); + s25f_legacy_software_reset(flash); + return -1; + } + + if (tmp & (1 << 6)) { + msg_cerr("Programming error occurred\n"); + s25f_legacy_software_reset(flash); + return -1; + } + + programmer_delay(1000 * 10); + tmp = spi_read_status_register(flash); + } + + return 0; +} + +/* "Read Any Register" instruction only supported on S25FS */ +static int s25fs_read_cr(const struct flashctx *flash, uint32_t addr) +{ + int result; + uint8_t cfg; + /* By default, 8 dummy cycles are necessary for variable-latency + commands such as RDAR (see CR2NV[3:0]). */ + unsigned char read_cr_cmd[] = { + CMD_RDAR, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff), + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + }; + + result = spi_send_command(flash, sizeof(read_cr_cmd), 1, read_cr_cmd, &cfg); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return -1; + } + + return cfg; +} + +static int s25f_read_cr1(const struct flashctx *flash) +{ + int result; + uint8_t cfg; + unsigned char read_cr_cmd[] = { CMD_RDCR }; + + result = spi_send_command(flash, sizeof(read_cr_cmd), 1, read_cr_cmd, &cfg); + if (result) { + msg_cerr("%s failed during command execution\n", __func__); + return -1; + } + + return cfg; +} + +/* "Write Any Register" instruction only supported on S25FS */ +static int s25fs_write_cr(const struct flashctx *flash, + uint32_t addr, uint8_t data) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = CMD_WRAR_LEN, + .writearr = (const unsigned char[]){ + CMD_WRAR, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff), + data + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return -1; + } + + programmer_delay(T_W); + return s25f_poll_status(flash); +} + +static int s25f_write_cr1(const struct flashctx *flash, uint8_t data) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = CMD_WRR_LEN, + .writearr = (const unsigned char[]){ + CMD_WRR, + spi_read_status_register(flash), + data, + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution\n", __func__); + return -1; + } + + programmer_delay(T_W); + return s25f_poll_status(flash); +} + +static int s25fs_restore_cr3nv(struct flashctx *flash, uint8_t cfg) +{ + int ret = 0; + + msg_cdbg("Restoring CR3NV value to 0x%02x\n", cfg); + ret |= s25fs_write_cr(flash, CR3NV_ADDR, cfg); + ret |= s25fs_software_reset(flash); + return ret; +} + +/* returns state of top/bottom block protection, or <0 to indicate error */ +static int s25f_get_tbprot_o(const struct flashctx *flash) +{ + int cr1 = s25f_read_cr1(flash); + + if (cr1 < 0) + return -1; + + /* + * 1 = BP starts at bottom (low address) + * 0 = BP start at top (high address) + */ + return cr1 & CR1_TBPROT_O ? 1 : 0; +} + +/* fills modifier_bits struct, returns 0 to indicate success */ +int s25f_get_modifier_bits(const struct flashctx *flash, + struct modifier_bits *m) +{ + int tmp; + + memset(m, 0, sizeof(*m)); + + tmp = s25f_get_tbprot_o(flash); + if (tmp < 0) + return -1; + m->tb = tmp; + + return 0; +} + +int s25f_set_modifier_bits(const struct flashctx *flash, + struct modifier_bits *m) +{ + int cr1, cr1_orig; + + cr1 = cr1_orig = s25f_read_cr1(flash); + if (cr1 < 0) + return -1; + + /* + * Clear BPNV so that setting BP2-0 in status register gets + * written to non-volatile memory. + * + * For TBPROT: + * 1 = BP starts at bottom (low address) + * 0 = BP start at top (high address) + */ + cr1 &= ~(CR1_BPNV_O | CR1_TBPROT_O); + cr1 |= m->tb ? CR1_TBPROT_O : 0; + + if (cr1 != cr1_orig) { + msg_cdbg("%s: setting cr1 bits to 0x%02x\n", __func__, cr1); + if (s25f_write_cr1(flash, cr1) < 0) + return -1; + if (s25f_read_cr1(flash) != cr1) { + msg_cerr("%s: failed to set CR1 value\n", __func__); + return -1; + } + } else { + msg_cdbg("%s: cr1 bits already match desired value: " + "0x%02x\n", __func__, cr1); + } + + return 0; +} + +int s25fs_block_erase_d8(struct flashctx *flash, + unsigned int addr, unsigned int blocklen) +{ + unsigned char cfg; + int result; + static int cr3nv_checked = 0; + + struct spi_command erase_cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_D8_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_D8, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + /* Check if hybrid sector architecture is in use and, if so, + * switch to uniform sectors. */ + if (!cr3nv_checked) { + cfg = s25fs_read_cr(flash, CR3NV_ADDR); + if (!(cfg & CR3NV_20H_NV)) { + s25fs_write_cr(flash, CR3NV_ADDR, cfg | CR3NV_20H_NV); + s25fs_software_reset(flash); + + cfg = s25fs_read_cr(flash, CR3NV_ADDR); + if (!(cfg & CR3NV_20H_NV)) { + msg_cerr("%s: Unable to enable uniform " + "block sizes.\n", __func__); + return 1; + } + + msg_cdbg("\n%s: CR3NV updated (0x%02x -> 0x%02x)\n", + __func__, cfg, + s25fs_read_cr(flash, CR3NV_ADDR)); + /* Restore CR3V when flashrom exits */ + register_chip_restore(s25fs_restore_cr3nv, flash, cfg); + } + + cr3nv_checked = 1; + } + + result = spi_send_multicommand(flash, erase_cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + + programmer_delay(S25FS_T_SE); + return s25f_poll_status(flash); +} + +int s25fl_block_erase(struct flashctx *flash, + unsigned int addr, unsigned int blocklen) +{ + int result; + + struct spi_command erase_cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_WREN + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_DC_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_DC, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .readcnt = 0, + } + }; + + result = spi_send_multicommand(flash, erase_cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + + programmer_delay(S25FL_T_SE); + return s25f_poll_status(flash); +} + + +int probe_spi_big_spansion(struct flashctx *flash) +{ + static const unsigned char cmd = JEDEC_RDID; + int ret; + unsigned char dev_id[6]; /* We care only about 6 first bytes */ + + ret = spi_send_command(flash, sizeof(cmd), sizeof(dev_id), &cmd, dev_id); + + if (!ret) { + for (size_t i = 0; i < sizeof(dev_id); i++) + msg_gdbg(" 0x%02x", dev_id[i]); + msg_gdbg(".\n"); + + if (dev_id[0] == flash->chip->manufacture_id) { + union { + uint8_t array[4]; + uint32_t whole; + } model_id; + + /* + * The structure of the RDID output is as follows: + * + * offset value meaning + * 00h 01h Manufacturer ID for Spansion + * 01h 20h 128 Mb capacity + * 01h 02h 256 Mb capacity + * 02h 18h 128 Mb capacity + * 02h 19h 256 Mb capacity + * 03h 4Dh Full size of the RDID output (ignored) + * 04h 00h FS: 256-kB physical sectors + * 04h 01h FS: 64-kB physical sectors + * 04h 00h FL: 256-kB physical sectors + * 04h 01h FL: Mix of 64-kB and 4KB overlayed sectors + * 05h 80h FL family + * 05h 81h FS family + * + * Need to use bytes 1, 2, 4, and 5 to properly identify one of eight + * possible chips: + * + * 2 types * 2 possible sizes * 2 possible sector layouts + * + */ + memcpy(model_id.array, dev_id + 1, 2); + memcpy(model_id.array + 2, dev_id + 4, 2); + if (be_to_cpu32(model_id.whole) == flash->chip->model_id) + return 1; + } + } + return 0; +} diff --git a/spi.h b/spi.h index c1ca46a..09da579 100644 --- a/spi.h +++ b/spi.h @@ -111,6 +111,11 @@ #define JEDEC_BE_D7_OUTSIZE 0x04 #define JEDEC_BE_D7_INSIZE 0x00 +/* Block Erase 0xdc is supported by Spansion chips, takes 4 byte address */ +#define JEDEC_BE_DC 0xdc +#define JEDEC_BE_DC_OUTSIZE 0x05 +#define JEDEC_BE_DC_INSIZE 0x00 + /* Sector Erase 0x20 is supported by Macronix/SST chips. */ #define JEDEC_SE 0x20 #define JEDEC_SE_OUTSIZE 0x04 @@ -129,6 +134,7 @@ /* Status Register Bits */ #define SPI_SR_WIP (0x01 << 0) #define SPI_SR_WEL (0x01 << 1) +#define SPI_SR_ERA_ERR (0x01 << 5) #define SPI_SR_AAI (0x01 << 6) /* Write Status Enable */ -- To view, visit https://review.coreboot.org/c/flashrom/+/46140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2d23f9c36ce8b2959807fbeee7f60e02444e3763 Gerrit-Change-Number: 46140 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

3 27

Change in flashrom[master]: WIP: flashrom: import chip restore handler from cros flashrom
by Nikolai Artemiev (Code Review) 03 Dec '20

03 Dec '20

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47276 ) Change subject: WIP: flashrom: import chip restore handler from cros flashrom ...................................................................... WIP: flashrom: import chip restore handler from cros flashrom Change-Id: I2a522dc1fd3952793fbcad70afc6dd43850fbbc5 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M flash.h M flashrom.c 2 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/76/47276/1 diff --git a/flash.h b/flash.h index 203d32d..a58f1a1 100644 --- a/flash.h +++ b/flash.h @@ -349,6 +349,8 @@ int do_erase(struct flashctx *); int do_write(struct flashctx *, const char *const filename, const char *const referencefile); int do_verify(struct flashctx *, const char *const filename); +#define CHIP_RESTORE_CALLBACK int (*func) (struct flashctx *flash, uint8_t status) +int register_chip_restore(CHIP_RESTORE_CALLBACK, struct flashctx *flash, uint8_t status); /* Something happened that shouldn't happen, but we can go on. */ #define ERROR_NONFATAL 0x100 diff --git a/flashrom.c b/flashrom.c index 26e2df8..c4b17bb 100644 --- a/flashrom.c +++ b/flashrom.c @@ -536,6 +536,15 @@ {0}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; +#define CHIP_RESTORE_MAXFN 4 +static int chip_restore_fn_count = 0; +static struct chip_restore_func_data { + CHIP_RESTORE_CALLBACK; + struct flashctx *flash; + uint8_t status; +} chip_restore_fn[CHIP_RESTORE_MAXFN]; + + #define SHUTDOWN_MAXFN 32 static int shutdown_fn_count = 0; /** @private */ @@ -580,6 +589,22 @@ return 0; } +int register_chip_restore(CHIP_RESTORE_CALLBACK, + struct flashctx *flash, uint8_t status) +{ + if (chip_restore_fn_count >= CHIP_RESTORE_MAXFN) { + msg_perr("Tried to register more than %i chip restore" + " functions.\n", CHIP_RESTORE_MAXFN); + return 1; + } + chip_restore_fn[chip_restore_fn_count].func = func; /* from macro */ + chip_restore_fn[chip_restore_fn_count].flash = flash; + chip_restore_fn[chip_restore_fn_count].status = status; + chip_restore_fn_count++; + + return 0; +} + int programmer_init(enum programmer prog, const char *param) { int ret; @@ -626,6 +651,19 @@ return ret; } +static int chip_restore() +{ + int rc = 0; + + while (chip_restore_fn_count > 0) { + int i = --chip_restore_fn_count; + rc |= chip_restore_fn[i].func(chip_restore_fn[i].flash, + chip_restore_fn[i].status); + } + + return rc; +} + /** Calls registered shutdown functions and resets internal programmer-related variables. * Calling it is safe even without previous initialization, but further interactions with programmer support * require a call to programmer_init() (afterwards). @@ -2286,6 +2324,7 @@ void finalize_flash_access(struct flashctx *const flash) { unmap_flash(flash); + chip_restore(); } /** -- To view, visit https://review.coreboot.org/c/flashrom/+/47276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2a522dc1fd3952793fbcad70afc6dd43850fbbc5 Gerrit-Change-Number: 47276 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

2 22

Change in flashrom[master]: chipset_enable.c: Validate physmap() return rcrb value
by Edward O'Callaghan (Code Review) 03 Dec '20

03 Dec '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48225 ) Change subject: chipset_enable.c: Validate physmap() return rcrb value ...................................................................... chipset_enable.c: Validate physmap() return rcrb value Validate the physical mapping in enable_flash_silvermont(). Change-Id: Icc5a799a06b3f310d9a191fa5eb99b255b20d79d Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M chipset_enable.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/25/48225/1 diff --git a/chipset_enable.c b/chipset_enable.c index 5e4a547..7c98798 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -996,6 +996,8 @@ /* Handle GCS (in RCRB) */ void *rcrb = physmap("BYT RCRB", rcba, 4); + if (rcrb == ERROR_PTR) + return ERROR_FATAL; const enum chipbustype boot_buses = enable_flash_ich_report_gcs(dev, ich_generation, rcrb); physunmap(rcrb, 4); -- To view, visit https://review.coreboot.org/c/flashrom/+/48225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Icc5a799a06b3f310d9a191fa5eb99b255b20d79d Gerrit-Change-Number: 48225 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 3

Change in flashrom[master]: flash.h: Trivial indent fix of comment
by Edward O'Callaghan (Code Review) 02 Dec '20

02 Dec '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48204 ) Change subject: flash.h: Trivial indent fix of comment ...................................................................... flash.h: Trivial indent fix of comment Align with the properly tab indented comment on the CrOS Flashrom side to make things consisent. Change-Id: I09605bfec203d294077f298f8619bbc7d10cc68a Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M flash.h 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/04/48204/1 diff --git a/flash.h b/flash.h index 203d32d..a1e7669 100644 --- a/flash.h +++ b/flash.h @@ -269,9 +269,10 @@ bool verify_whole_chip; } flags; /* We cache the state of the extended address register (highest byte - of a 4BA for 3BA instructions) and the state of the 4BA mode here. - If possible, we enter 4BA mode early. If that fails, we make use - of the extended address register. */ + * of a 4BA for 3BA instructions) and the state of the 4BA mode here. + * If possible, we enter 4BA mode early. If that fails, we make use + * of the extended address register. + */ int address_high_byte; bool in_4ba_mode; }; -- To view, visit https://review.coreboot.org/c/flashrom/+/48204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I09605bfec203d294077f298f8619bbc7d10cc68a Gerrit-Change-Number: 48204 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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flashrom-gerrit December 2020