[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/skylake: Enable 4E/4F PNP I/O ports in bootblock

[Paul Menzel (Code Review)]

Attention is currently required from: Máté Kukri.

Paul Menzel has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/85273?usp=email )

Change subject: soc/intel/skylake: Enable 4E/4F PNP I/O ports in bootblock
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Patch Set 1:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/85273/comment/cf0fa619_bd3f9cab?usp... :
PS1, Line 8:
> The ThinkPad T480's Embedded Controller exposes it's PNP interface at this address pair. […]

It’d be great, if you copied your answer to the commit message.