Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34724 )
Change subject: soc/intel/common: Implement power-failure-state handling ......................................................................
soc/intel/common: Implement power-failure-state handling
This is a consolidation of the respective feature in `soc/intel/*lake/`, including additional support for MAINBOARD_POWER_STATE_PREVIOUS.
For the latter, firmware has to keep track of the `previous` state. The feature was already advertised in Kconfig long ago, but not implemented.
SoC code has to call pmc_set_power_failure_state() at least once during boot and needs to implement pmc_soc_set_afterg3_en() for the actual register write.
Change-Id: Ic6970a79d9b95373c2855f4c92232d2aa05963bb Signed-off-by: Nico Huber nico.h@gmx.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/34724 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 44 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index 82eb2ae..8947a22 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -16,6 +16,7 @@ #ifndef SOC_INTEL_COMMON_BLOCK_PMCLIB_H #define SOC_INTEL_COMMON_BLOCK_PMCLIB_H
+#include <device/pci_type.h> #include <stdint.h>
/* Forward declare the power state struct here */ @@ -214,4 +215,20 @@ MAINBOARD_POWER_STATE_PREVIOUS, };
+/* + * Implemented by SoC code to set PMC register to know which state + * system should go into after power is reapplied. + */ +void pmc_soc_set_afterg3_en(bool on); +/* + * Configure power state to go into when power is reapplied. + * + * To be called by SoC code once during boot and will be called by + * the "sleep" SMI handler when going into S5. + * + * `target_on` signifies that we are currently powering on, so that + * MAINBOARD_POWER_STATE_PREVIOUS can be handled accordingly. + */ +void pmc_set_power_failure_state(bool target_on); + #endif /* SOC_INTEL_COMMON_BLOCK_PMCLIB_H */ diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 564aacb..ee99735 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -579,3 +579,30 @@ /* Set the routes in the GPIO communities as well. */ gpio_route_gpe(dw0, dw1, dw2); } + +void pmc_set_power_failure_state(const bool target_on) +{ + const int state = CONFIG_MAINBOARD_POWER_FAILURE_STATE; + bool on; + + switch (state) { + case MAINBOARD_POWER_STATE_OFF: + printk(BIOS_INFO, "Set power off after power failure.\n"); + on = false; + break; + case MAINBOARD_POWER_STATE_ON: + printk(BIOS_INFO, "Set power on after power failure.\n"); + on = true; + break; + case MAINBOARD_POWER_STATE_PREVIOUS: + printk(BIOS_INFO, "Keep power state after power failure.\n"); + on = target_on; + break; + default: + printk(BIOS_WARNING, "WARNING: Unknown power-failure state: %d\n", state); + on = false; + break; + } + + pmc_soc_set_afterg3_en(on); +}