[coreboot-gerrit] [S] Change in coreboot[main]: mb/prodrive/atlas: Remove the workaround for CLKREQ pins

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79021?usp=email )

(

3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: mb/prodrive/atlas: Remove the workaround for CLKREQ pins
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mb/prodrive/atlas: Remove the workaround for CLKREQ pins

As Intel has provided fixes regarding CLKREQ pins issue with new
UPD settings as described in commit b8abde7a8ef4
("soc/intel/alderlake: Disable PCIe clock gating"), remove this
WA as introduced by this commit 586b1c8da06f
("mb/prodrive/atlas: Add workaround for CLKREQ pins").

Signed-off-by: Lean Sheng Tan 
Change-Id: Icbab617428551accda66499b7c2a32b2fa8c1689
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79021
Reviewed-by: Paul Menzel 
Reviewed-by: Matt DeVillier 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/prodrive/atlas/romstage_fsp_params.c
1 file changed, 0 insertions(+), 26 deletions(-)

Approvals:
  Matt DeVillier: Looks good to me, approved
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve

diff --git a/src/mainboard/prodrive/atlas/romstage_fsp_params.c b/src/mainboard/prodrive/atlas/romstage_fsp_params.c
index ab47dd0..7d3d9b5 100644
--- a/src/mainboard/prodrive/atlas/romstage_fsp_params.c
+++ b/src/mainboard/prodrive/atlas/romstage_fsp_params.c
@@ -72,30 +72,4 @@
    mcfg->CpuPcieRpClockReqMsgEnable[0] = 0;
    mcfg->CpuPcieRpClockReqMsgEnable[1] = 0;
    mcfg->CpuPcieRpClockReqMsgEnable[2] = 0;
-
-	// shared clock
-	mcfg->PcieClkSrcUsage[0] = 0x80;
-	mcfg->PcieClkSrcClkReq[0] = 0xFF;
-	// i225
-	mcfg->PcieClkSrcUsage[1] = 9; // RP 10
-	mcfg->PcieClkSrcClkReq[1] = 1;
-
-	// FIX Apparently Rootports don't like the idea of not having a clksrc and clkreq
-	// attached to it. For example if we set PcieClkSrcClkReq[1] above to 0xFF (unused)
-	// it will not come back out of L1. You can easily test this on windows by trying to
-	// update the i225 driver in device manager or use setpci in Linux to set Device in D3.
-	// The same applies to all other rootports no matter which devices are connected to it.
-	// Therefore we put each rootport (that does not have a clkreq, clksrc)
-	// to a not connected (not routed out) clksrc and clkreq. That seems to be a current FSP Bug.
-	// workaround and will be removed as soon as FSP is fixed.
-	mcfg->PcieClkSrcUsage[2] = 4; // Rootport 5
-	mcfg->PcieClkSrcClkReq[2] = 0;
-	mcfg->PcieClkSrcUsage[3] = 5; // Rootport 6
-	mcfg->PcieClkSrcClkReq[3] = 0;
-	mcfg->PcieClkSrcUsage[4] = 8; // Rootport 9
-	mcfg->PcieClkSrcClkReq[4] = 0;
-	mcfg->PcieClkSrcUsage[5] = 6; // Rootport 7
-	mcfg->PcieClkSrcClkReq[5] = 0;
-	mcfg->PcieClkSrcUsage[6] = 7; // Rootport 8
-	mcfg->PcieClkSrcClkReq[6] = 0;
 }