Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43428 )
Change subject: soc/amd/picasso/acpi,mb/{zork,mandolin}: Stop clearing PciExpWakeStatus ......................................................................
soc/amd/picasso/acpi,mb/{zork,mandolin}: Stop clearing PciExpWakeStatus
The kernel already clears this: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/th... No reason to have the firmware do it as well.
BUG=b:153001807, b:154756391 TEST=Build Trembyle, boot, suspend, and resume and didn't see any ACPI errors.
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ia5c79fb95dc885eaef8abc4257b6ba18c1ef1b66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43428 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/amd/mandolin/acpi/sleep.asl M src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sleep.asl M src/soc/amd/picasso/acpi/pcie.asl 3 files changed, 0 insertions(+), 22 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/amd/mandolin/acpi/sleep.asl b/src/mainboard/amd/mandolin/acpi/sleep.asl index 6fdb30b..526754e 100644 --- a/src/mainboard/amd/mandolin/acpi/sleep.asl +++ b/src/mainboard/amd/mandolin/acpi/sleep.asl @@ -21,8 +21,6 @@ /* DBGO("From S0 to S") */ /* DBGO(Arg0) */ /* DBGO("\n") */ - - Store(0, PEWD) } /* End Method(_PTS) */
/* diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sleep.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sleep.asl index 267be30..4a62ecf 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sleep.asl +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sleep.asl @@ -21,8 +21,6 @@ /* DBGO("From S0 to S") */ /* DBGO(Arg0) */ /* DBGO("\n") */ - - Store(0, PEWD) } /* End Method(_PTS) */
/* diff --git a/src/soc/amd/picasso/acpi/pcie.asl b/src/soc/amd/picasso/acpi/pcie.asl index cb4be7f..601de52 100644 --- a/src/soc/amd/picasso/acpi/pcie.asl +++ b/src/soc/amd/picasso/acpi/pcie.asl @@ -63,21 +63,3 @@ IUA2, 0x00000008, /* Index 0xF8: UART2 */ IUA3, 0x00000008, /* Index 0xF9: UART3 */ } - - /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ - OperationRegion(PIOR, SystemIO, 0x00000Cd6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x60), /* AcpiPm1EvgBlk */ - P1EB, 16, - } - OperationRegion (P1E0, SystemIO, P1EB, 0x04) - Field (P1E0, ByteAcc, Nolock, Preserve) { - Offset(0x02), - , 14, - PEWD, 1, - }