[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Enable IRQ routing

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu.

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84328?usp=email )

Change subject: soc/intel/xeon_sp/gnr: Enable IRQ routing
......................................................................

soc/intel/xeon_sp/gnr: Enable IRQ routing

Enable IRQ routing per PCH IRQ usage convention and report domain
_PRT.

Change-Id: I095c7a302894437c90d854ce4e30467357eee2ba
Signed-off-by: Lu, Pen-ChunX 
---
M src/soc/intel/xeon_sp/gnr/chip.c
M src/soc/intel/xeon_sp/gnr/soc_acpi.c
2 files changed, 21 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/84328/1

diff --git a/src/soc/intel/xeon_sp/gnr/chip.c b/src/soc/intel/xeon_sp/gnr/chip.c
index 45a0173..a101b93 100644
--- a/src/soc/intel/xeon_sp/gnr/chip.c
+++ b/src/soc/intel/xeon_sp/gnr/chip.c
@@ -1,10 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <bootstate.h>
+#include <intelblocks/itss.h>
 #include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
 #include <intelblocks/pmclib.h>
-#include <soc/pm.h>
 #include <soc/chip_common.h>
 #include <soc/numa.h>
+#include <soc/pcr_ids.h>
+#include <soc/pm.h>
 #include <soc/ramstage.h>

#include "chip.h"
@@ -53,3 +57,16 @@
 {
    mainboard_silicon_init_params(silupd);
 }
+
+static void pirq_init(void *unused)
+{
+	/* Program irq pin/line for PCI devices by PCH convention */
+	pch_pirq_init();
+
+	/* Explicitly set polarity low for PIRQA to PIRQH */
+	for (int i = 0; i < PIRQ_COUNT; i++) {
+		itss_set_irq_polarity(pcr_read8(PID_ITSS, PCR_ITSS_PIRQA_ROUT + i), 1);
+	}
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, pirq_init, NULL);
diff --git a/src/soc/intel/xeon_sp/gnr/soc_acpi.c b/src/soc/intel/xeon_sp/gnr/soc_acpi.c
index 54c0cd2..76fabd2 100644
--- a/src/soc/intel/xeon_sp/gnr/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/gnr/soc_acpi.c
@@ -84,6 +84,9 @@
    acpigen_write_name("_PXM");
    acpigen_write_integer(device_to_pd(domain));

+	/* _PRT */
+	acpigen_write_PRT_pre_routed(domain);
+
    /* _OSC */
    acpigen_write_OSC_pci_domain_fixed_caps(domain,
    	get_granted_pcie_features(),