[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Use PMC IPC to disable HECI1

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61457 )

Change subject: soc/intel/tigerlake: Use PMC IPC to disable HECI1
......................................................................

soc/intel/tigerlake: Use PMC IPC to disable HECI1

This patch allows common CSE block to disable HECI1 device using PMC
IPC command `0xA9`.

Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for
Tiger Lake to disable HECI1 device using PMC IPC.

Additionally, remove dead code that deals with HECI1 disabling using
in SMM as HECI1 disabling using PMC IPC is simpler solution.

BUG=none
TEST=None

Signed-off-by: Subrata Banik 
Change-Id: Id5f1e3f622f65cd0f892c0dc541625bfd50d038e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61457
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/finalize.c
M src/soc/intel/tigerlake/smihandler.c
3 files changed, 4 insertions(+), 15 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index b324a04..7a8b01b 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -60,6 +60,7 @@
    select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY
    select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
    select SOC_INTEL_COMMON_BLOCK_HDA
+	select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT
    select SOC_INTEL_COMMON_BLOCK_IRQ
    select SOC_INTEL_COMMON_BLOCK_MEMINIT
    select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
@@ -84,7 +85,6 @@
    select UDELAY_TSC
    select UDK_2017_BINDING
    select DISPLAY_FSP_VERSION_INFO
-	select HECI_DISABLE_USING_SMM

config MAX_CPUS
    int
diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c
index b50529b..1067278 100644
--- a/src/soc/intel/tigerlake/finalize.c
+++ b/src/soc/intel/tigerlake/finalize.c
@@ -12,6 +12,7 @@
 #include <cpu/x86/smm.h>
 #include <device/mmio.h>
 #include <device/pci.h>
+#include <intelblocks/cse.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/pmclib.h>
@@ -64,6 +65,8 @@
    apm_control(APM_CNT_FINALIZE);
    tbt_finalize();
    sa_finalize();
+	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
+		heci1_disable();

/* Indicate finalize step with post code */
    post_code(POST_OS_BOOT);
diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c
index 843733f..e1fc5a0 100644
--- a/src/soc/intel/tigerlake/smihandler.c
+++ b/src/soc/intel/tigerlake/smihandler.c
@@ -1,25 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <device/pci_def.h>
-#include <intelblocks/cse.h>
 #include <intelblocks/smihandler.h>
 #include <soc/soc_chip.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>

-/*
- * Specific SOC SMI handler during ramstage finalize phase
- *
- * BIOS can't make CSME function disable as is due to POSTBOOT_SAI
- * restriction in place from TGP chipset. Hence create SMI Handler to
- * perform CSME function disabling logic during SMM mode.
- */
-void smihandler_soc_at_finalize(void)
-{
-	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM))
-		heci1_disable();
-}
-
 int smihandler_soc_disable_busmaster(pci_devfn_t dev)
 {
    /* Skip disabling PMC bus master to keep IO decode enabled */