[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table

[Subrata Banik (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams.

Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email )

Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
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Patch Set 3:

(1 comment)

File src/soc/intel/common/block/acpi/acpi.c:

https://review.coreboot.org/c/coreboot/+/84103/comment/39abef01_50206d52?usp... :
PS3, Line 110: SOC_INTEL_COMMON_BLOCK_ACPI_GPE1
suggestion, looks like we don't need a CPP if we follow the below method

1. As ACPI spec, if platform doesn't support `gpe1_blk` then this field should be zero.

2. Define GPE1_STS` for all non-supported SoC as below

```
/* Platform doesn't have support for GPE1, adding dummy entry for common code */
#define  GPE1_STS(x)		(0x0 + ((x) * 4))
```

3. Only supported SoC like PTL would implement something like this

```
#define  GPE1_STS(x)		(0x10 + ((x) * 4))
```

4.  update this logic w/o any need for CPP

```
    fadt->gpe1_blk =  GPE1_STS(0) ? (pmbase + GPE1_STS(0)) :  GPE1_STS(0);
    if (!fadt->gpe1_blk) {
      fadt->gpe1_blk_len = 2 * GPE1_REG_MAX * sizeof(uint32_t);
      /*
       * NOTE: gpe1 is after gpe0, which has _STS and _EN register sets.
       * gpe1_base is the starting bit offset for GPE1.
       */
       fadt->gpe1_base = fadt->gpe0_blk_len / 2 * 8;
    }
```