Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47234 )
Change subject: sb/intel/lynxpoint: Correct SATA DTLE IOBP registers ......................................................................
Patch Set 1: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/47234/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47234/1//COMMIT_MSG@9 PS1, Line 9: Testing Would be nice to elaborate on the testing. Could you break functionality on a given port with a different value?
https://review.coreboot.org/c/coreboot/+/47234/1/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/pch.h:
https://review.coreboot.org/c/coreboot/+/47234/1/src/southbridge/intel/lynxp... PS1, Line 275: #define SATA_DTLE_MASK 0xF BIOS spec suggests this should be 0x3f