Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36567 )
Change subject: soc/intel/cannonlake: add soc implementation for ETR address API ......................................................................
soc/intel/cannonlake: add soc implementation for ETR address API
Add soc implementation for the new ETR address API.
Change-Id: Ifc128099185a2c40ec3e7c5f84fcc42227c93f28 Signed-off-by: Michael Niewöhner foss@mniewoehner.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/36567 Reviewed-by: Aaron Durbin adurbin@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/cannonlake/pmutil.c 1 file changed, 5 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index a543861..428a89f 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -172,6 +172,11 @@ return (uintptr_t)pmc_mmio_regs(); }
+uint32_t *soc_pmc_etr_addr(void) +{ + return (uint32_t *)(soc_read_pmc_base() + ETR); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_cannonlake_config *config;