[coreboot-gerrit] [S] Change in coreboot[main]: mb/ocp/tiogapass: Wait for BMC

[Patrick Rudolph (Code Review)]

Attention is currently required from: Johnny Lin, Morgan Jang.

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85492?usp=email )

Change subject: mb/ocp/tiogapass: Wait for BMC
......................................................................

mb/ocp/tiogapass: Wait for BMC

The mainboard code relies on IPMI communication with the BMC.

Since the x86 and BMC start booting at the same time on ACPI G3
exit and the x86 is a bit faster, wait for the BMC to signal it's
done booting by pulling GPP_F4 low.

Fixes lot's of error messages about not working IPMI.

TEST: Once GPP_F4 is low IPMI communication over the KCS is also
      working on ocp/tiogapass.

Change-Id: I925aff1ff1ffd3d7388835e62aad2ba339e52472
Signed-off-by: Patrick Rudolph 
---
M src/mainboard/ocp/tiogapass/romstage.c
1 file changed, 26 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/85492/1

diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c
index 283d5f1..a72a37d 100644
--- a/src/mainboard/ocp/tiogapass/romstage.c
+++ b/src/mainboard/ocp/tiogapass/romstage.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */

+#include <delay.h>
 #include <drivers/ipmi/ipmi_if.h>
 #include <drivers/ipmi/ocp/ipmi_ocp.h>
 #include <fsp/api.h>
@@ -10,6 +11,7 @@
 #include <soc/romstage.h>
 #include <string.h>
 #include <skxsp_tp_iio.h>
+#include <timer.h>

#include "ipmi.h"

@@ -52,8 +54,32 @@
    oem_update_iio(mupd);
 }

+static void mainboard_wait_for_bmc_ready(void)
+{
+	struct stopwatch sw;
+	static const long timeout = 180 * 1000;
+
+	printk(BIOS_DEBUG, "Waiting for BMC ready\n");
+	gpio_input(GPP_F4);
+
+	stopwatch_init_msecs_expire(&sw, timeout);
+	while (gpio_get(GPP_F4)) {
+		if (stopwatch_expired(&sw)) {
+			printk(BIOS_WARNING,
+			       "BMC not ready after %ldms. Abort.\n", timeout);
+			return;
+		}
+		mdelay(100);
+	}
+	printk(BIOS_DEBUG, "BMC ready after %lld ms\n",
+	       stopwatch_duration_msecs(&sw));
+}
+
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
+	/* Need to wait for BMC ready so that IPMI works. */
+	mainboard_wait_for_bmc_ready();
+
    /* It's better to run get BMC selftest result first */
    if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) {
    	ipmi_set_post_start(CONFIG_BMC_KCS_BASE);